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09005aef8071a76b 128mbx16x32mobile_1.fm - rev. j 7/04 en 1 ?2001 micron technology, inc. all rights reserved. 128mb: x16, x32 mobile sdram synchronous dram mt48lc8m16lff4, mt48v8m16lff4, mt48lc8m16tg, mt48v8m16tg, mt48v8m16p, mt48lc4m32lff5, mt48v4m32lff5 features ? temperature compensated self refresh (tcsr) fully synchronous; all signals registered on positive edge of system clock internal pipelined operation; column address can be changed every clock cycle internal banks for hiding row access/precharge programmable burst length s: 1, 2, 4, 8, or full page auto precharge, includes concurrent auto precharge, and auto refresh modes self refresh mode; standard and low power 64ms, 4,096-cycle refresh lvttl-compatible inputs and outputs low voltage power supply partial array self refresh power-saving mode note: 1. x16 only. 2. x32 only. part number example: mt48v8m16lfb5-8 options marking v dd /v dd q 3.3v/3.3v lc 2.5v/2.5v ? 1.8v v configurations 8 meg x 16 (2 meg x 16 x 4 banks) 8m16 4 meg x 32 (1 meg x 32 x 4 banks) 4m32 package/ball out 54-ball vfbga (8mm x 8mm) 1 f4 54-ball vfbga (8mm x 8mm) 1 lead-free b4 90-ball vfbga (8mm x 13mm) 2 f5 90-ball vfbga (8mm x 13mm) 2 lead-free b5 54-pin tsop ii (400 mil) tg 54-pin tsop ii (400 mil) lead-free p timing (cycle time) 7.5ns @ cl = 3 (133 mhz) -75m 8ns @ cl = 3 (125 mhz) -8 10ns @ cl = 3 (100 mhz) -10 temperature commercial (0c to +70c) none industrial (-40c to +85c) it extended (-25c to +75c) xt table 1: configurations 8 meg x 16 4 meg x 32 configuration 2 meg x 16 x 4 banks 1 meg x 32 x 4 banks refresh count 4k 4k row addressing 4k (a0?a11) 4k (a0?a11) bank addressing 4 (ba0, ba1) 4 (ba0, ba1) column addressing 512 (a0?a8) 256 (a0?a7) table 2: key timing parameters cl = cas (read) latency speed grade clock frequency access time t rcd t rp cl = 1 cl = 2 cl = 3 -75m 133mhz - - 5.4 19ns 19ns -8 125 mhz ? ? 7ns 20ns 20ns -10 100 mhz ? ? 7ns 20ns 20ns -75m 100mhz - 6 - 19ns 19ns -8 100 mhz ? 8ns ? 20ns 20ns -10 83 mhz ? 8ns ? 20ns 20ns -8 50 mhz 19ns ? ? 20ns 20ns -10 40 mhz 22ns ? ? 20ns 20ns
128mb: x16, x32 mobile sdram 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobiletoc.fm - rev. g (draft) 7/04 en 2 ?2001 micron technology, inc. all rights reserved. table of contents features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 fbga part marking decoder. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 mode register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 burst length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 burst type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 cas latency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 write burst mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 operating mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 extended mode register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 temperature compensated self refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 partial array self refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 command inhibit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 no operation (nop) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 load mode register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 active. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 precharge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 auto precharge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 burst terminate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 auto refresh. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 self refresh. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 bank/row activation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 precharge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 clock suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 burst read/single write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 concurrent auto precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
128mb: x16, x32 mobile sdram 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobilelof.fm - rev. g (draft) 7/04 en 3 ?2001 micron technology, inc. all rights reserved. list of figures figure 1: 90-ball fbga pin assignment (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 figure 2: 54-pin tsop pin assignment (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 figure 3: 54-ball fbga and 54-ball vfbga pin assignment (top vi ew) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 figure 4: 128mb sdram part numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 figure 5: functional block diagram 8 meg x 16 sdram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 figure 6: functional block diagram 4 meg x 32 sdram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 figure 7: mode register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 figure 8: cas latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 figure 9: extended mode register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 figure 10: activating a specific row in a specific bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 figure 11: example: meeting trcd (min) when 2 < trcd (min)/tck< 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 figure 12: read command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 figure 13: cas latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 figure 14: consecutive read bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 figure 15: random read accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 figure 16: read to write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 figure 17: read to write with extra clock cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 figure 18: read to precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 figure 19: terminating a read burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 figure 20: write command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 figure 21: write burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 figure 22: write to write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 figure 23: random write cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 figure 24: write to read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 figure 25: write to precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 figure 26: terminating a write burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 figure 27: precharge command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 figure 28: power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 figure 29: clock suspend during write burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 figure 30: clock suspend during read burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 figure 31: read with auto precharge interrupted by a read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 figure 32: read with auto precharge interrupted by a write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 figure 33: write with auto precharge interrupted by a read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 figure 34: write with auto precharge interrupted by a write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 figure 35: initialize and load mode register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 figure 36: power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 figure 37: clock suspend mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 figure 38: auto refresh mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 figure 39: self refresh mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 figure 40: read ? without auto precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 figure 41: read ? with auto precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 figure 42: single read ? without auto precharge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 figure 43: single read ? with auto precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 figure 44: alternating bank read accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 figure 45: read ? full-page burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 figure 46: read ? dqm operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 figure 47: write ? without auto precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 figure 48: write ? with auto precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 figure 49: single write ? without auto precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 figure 50: single write ? with auto precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 figure 51: alternating bank write accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 figure 52: write ? full-page burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 figure 53: write ? dqm operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 figure 54: 54-ball vfbga (8mm x 8mm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 figure 55: 90-ball vfbga (8mm x 13mm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 figure 56: 54-pin plastic tsop (400 mil). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
128mb: x16, x32 mobile sdram 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobilelot.fm - rev. g (draft) 7/04 en 4 ?2001 micron technology, inc. all rights reserved. list of tables table 1: configurations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 table 2: key timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 table 3: ball descriptions: 54-ball vfbga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 table 4: ball descriptions: 90-ball vfbga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 table 5: pin descriptions: 54-pin tsop (x16 only). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 table 6: burst definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 table 7: cas latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 table 8: truth table?commands and dqm operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 table 9: truth table ? cke. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 table 10: truth table ? current state bank n , command to bank n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 table 11: truth table ? current state bank n, command to bank m. . . . . . . . . . . . . . . . . . . . . . . . . . . .40 table 12: dc electrical characteristics and operating conditions (lc version). . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 13: dc electrical characteristics and operating conditions (v version) . . . . . . . . . . . . . . . . . . . . . . . . . . .42 table 14: electrical characteristics and recommended ac operating conditions . . . . . . . . . . . . . . . . . . . . . . .43 table 15: ac functional characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 table 16: i dd specifications and conditions (x16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 table 17: i dd 7 self refresh current options (x16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 table 18: i dd specifications and conditions (x32) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 table 19: i dd 7 self refresh current options (x32) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 table 20: capacitance (fbga pacakge) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 table 21: capacitance (tsop pacakge) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
128mb: x16, x32 mobile sdram 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobile_2.fm - rev. g (draft) 7/04 en 5 ?2001 micron technology, inc. all rights reserved. figure 1: 90-ball fbga pin assignment (top view) figure 2: 54-pin tsop pin assignment (top view) figure 3: 54-ball fbga and 54-ball vfbga pin assignment (top view) 1234 6789 5 dq26 dq28 v ss q v ss q v dd q v ss a4 a7 clk dqm1 v dd q v ss q v ss q dq11 dq13 dq24 v dd q dq27 dq29 dq31 dqm3 a5 a8 cke nc dq8 dq10 dq12 v dd q dq15 v ss v ss q dq25 dq30 nc a3 a6 nc a9 nc v ss dq9 dq14 v ss q v ss v dd v dd q dq22 dq17 nc a2 a10 nc ba0 cas# v dd dq6 dq1 v dd q v dd dq21 dq19 v dd q v dd q v ss q v dd a1 a11 ras# dqm0 v ss q v dd q v dd q dq4 dq2 dq23 v ss q dq20 dq18 dq16 dqm2 a0 ba1 cs# we# dq7 dq5 dq3 v ss q dq0 a b c d e f g h j k l m n p r v dd dq0 v dd q dq1 dq2 vssq dq3 dq4 v dd q dq5 dq6 vssq dq7 v dd dqml we# cas# ras# cs# ba0 ba1 a10 a0 a1 a2 a3 v dd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 vss dq15 vssq dq14 dq13 v dd q dq12 dq11 vssq dq10 dq9 v dd q dq8 vss nc dqmh clk cke nc a11 a9 a8 a7 a6 a5 a4 vss x16 x16 note: the # symbol indicates signal is active low. a b c d e f g h j 1 2 3 4 5 6 7 8 top view (ball down) v ss dq14 dq12 dq10 dq8 udqm nc/a12 a8 v ss dq15 dq13 dq11 dq9 nc clk a11 a7 a5 v ss q v dd q v ss q v dd q v ss cke a9 a6 a4 v dd q v ss q v dd q v ss q v dd cas# ba0 a0 a3 dq0 dq2 dq4 dq6 ldqm ras# ba1 a1 a2 v dd dq1 dq3 dq5 dq7 we# cs# a10 v dd 9
128mb: x16, x32 mobile sdram 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobile_2.fm - rev. g (draft) 7/04 en 6 ?2001 micron technology, inc. all rights reserved. figure 4: 128mb sdram part numbers note: not all speeds and configurations are avail- able. fbga part marking decoder due to space limitations, fbga-packaged compo- nents have an abbreviated part marking that is differ- ent from the part number. micron's new fbga part marking decoder makes it easier to understand that part marking. visit the web site at www.micron.com/ decoder . general description the micron? 128mb sdram is a high-speed cmos, dynamic random-access memory containing 134,217,728 bits. it is internally configured as a quad- bank dram with a synchronous interface (all signals are registered on the positive edge of the clock signal, clk). each of the x16?s 33,554,432-bit banks is orga- nized as 4,096 rows by 512 columns by 16 bits. each of the x32?s 33,554,432-bit banks is organized as 4,096 rows by 256 columns by 32 bits. read and write accesses to the sdram are burst ori- ented; accesses start at a selected location and con- tinue for a programmed number of locations in a programmed sequence. accesses begin with the regis- tration of an active command, which is then fol- lowed by a read or write command. the address bits registered coincident with the active command are used to select the bank and row to be accessed (ba0, ba1 select the bank; a0 -a11) select the row). the address bits registered coincident with the read or write command are used to select the starting col- umn location for the burst access. the sdram provides for programmable read or write burst lengths of 1, 2, 4, or 8 locations, or the full page, with a burst terminate option. an auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. the 128mb sdram uses an internal pipelined architecture to achieve high-speed operation. this architecture is compatible with the 2 n rule of prefetch architectures, but it also allows the column address to be changed on every clock cycle to achieve a high- speed, fully random access. precharging one bank while accessing one of the other three banks will hide the precharge cycles and provide seamless high-speed, random-access operation. the 128mb sdram is designed to operate in 3.3v or 2.5v low-power memory systems. the 2.5v version is compatible with 1.8v i/o interface. an auto refresh - configuration mt48 package speed temperature configuration 8 meg x 16 4 meg x 32 8m16 4m32 package 54-ball fbga (8x8mm) 54-ball fbga (8x8mm) lead-free 90-ball vfbga (8x13mm) 90-ball vfbga (8x13mm ) lead-free 54-pin tsop ii (400 mil) 54-pin tsop ii (400 mil) lead-free it xt operating temp standard industrial temp extended temp example part number: mt48v4m32lff5-10xt voltage ( v dd /v dd q ) 3.3v/ 3.3v 2.5v / 2.5v - 1.8v lc v v dd / v dd q lf speed grade t ck=7.5ns, cl = 3 t ck=8ns, cl = 3 t ck=10ns, cl = 3 -75m -8 -10 f4 b4 f5 b5 tg p
128mb: x16, x32 mobile sdram 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobile_2.fm - rev. g (draft) 7/04 en 7 ?2001 micron technology, inc. all rights reserved. mode is provided, along with a power-saving, power- down mode. all inputs and outputs are lvttl-com- patible. sdrams offer substantial advances in dram oper- ating performance, including the ability to synchro- nously burst data at a high data rate with automatic column-address generation, the ability to interleave between internal banks in order to hide precharge time and the capability to randomly change column addresses on each clock cycle during a burst access. figure 5: functional block diagram 8 meg x 16 sdram 12 ras# cas# row- address mux clk cs# we# cke control logic column- address counter/ latch mode register 9 command decode a0-a11, ba0, ba1 dqml, dqmh 12 address register 14 512 (x16) 4096 i/o gating dqm mask logic read data latch write drivers column decoder bank0 memory array (4,096 x 512 x 16) bank0 row- address latch & decoder 4096 sense amplifiers bank control logic dq0- dq15 16 data input register data output register 16 12 bank1 bank2 bank3 12 9 2 2 2 2 refresh counter 16
128mb: x16, x32 mobile sdram 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobile_2.fm - rev. g (draft) 7/04 en 8 ?2001 micron technology, inc. all rights reserved. figure 6: functional block diagram 4 meg x 32 sdram 12 ras# cas# clk cs# we# cke 8 a0?a11, ba0, ba1 dqm0? dqm3 14 256 (x32) 4096 i/o gating dqm mask logic read data latch write drivers column decoder bank0 memory array (4,096 x 256 x 32) bank0 row- address latch & decoder 4096 sense amplifiers bank control logic dq0? dq31 32 data input register data output register 32 bank1 bank0 bank2 bank3 12 8 2 4 4 2 refresh counter 12 12 mode register control logic command decode row- address mux address register column- address counter/ latch 32
128mb: x16, x32 mobile sdram 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobile_2.fm - rev. g (draft) 7/04 en 9 ?2001 micron technology, inc. all rights reserved. table 3: ball descriptions: 54-ball vfbga 54-ball vfbga symbol type description f2 clk input clock: clk is driven by the system clock. all sdram input signals are sampled on the positive edge of clk. clk also increments the internal burst counter and controls the output registers. f3 cke input clock enable: cke activates (high) and deactivates (low) the clk signal. deactivating the clock provides precharge power-down and self refresh operation (all banks idle), active power-down (row active in any bank) or clock suspend operation (burst/access in progress). cke is synchronous except after the device enters power-down and self refresh modes, where cke becomes asynchro nous until after exiting the same mode. the input buffers, including clk, are disabled during power-down and self refresh modes, providing low standby power. cke may be tied high. g9 cs# input chip select: cs# enables (registered low) and disables (registered high) the command decoder. all commands are masked when cs# is registered high. cs# provides for external bank selection on systems with multiple banks. cs# is considered part of the command code. f7, f8, f9 cas#, ras#, we# input command inputs: cas#, ras#, and we# (along with cs#) define the command being entered. e8, f1 ldqm, udqm input input/output mask: dqm is sampled high and is an input mask signal for write accesses and an output enable signal for read accesses. input data is masked during a write cycle. the output buffers are placed in a high-z state (two-clock latency) when duri ng a read cycle. ldqm corresponds to dq0?dq7, udqm corresponds to dq8?dq15. ldqm and udqm are considered same state when referenced as dqm. g7, g8 ba0, ba1 input bank address input(s): ba0 and ba1 define to which bank the active, read, write or precharge command is being applied. these pins also provide the op-code during a load mode register command h7, h8, j8, j7, j3, j2, h3, h2, h1, g3, h9, g2 a0?a6 a7-a11 input address inputs: a0?a11 are sampled during the active command (row- address a0?a11) and read/write command (column-address a0?a8; with a10 defining auto precharge) to select one location out of the memory array in the respective bank. a10 is sampled during a precharge command to determine if all banks are to be precharged (a10 high) or bank selected by ba0, ba1 (low). the address inputs also provide the op-code during a load mode register command. a8, b9, b8, c9, c8, d9, d8, e9, e1, d2, d1, c2, c1, b2, b1, a2 dq0?dq5 dq6-dq11 dq12-dq15 i/o data input/output: data bus e2, g1 nc ? no connect: these pins should be left unconnected. g1 is a no connect for this part but may be used as a12 in future designs. a7, b3, c7, d3 v dd q supply dq power: isolated dq power on the die to improve noise immunity. a3, b7, c3, d7, v ss q supply dq ground: isolated dq power on the die to improve noise immunity. a9, e7, j9 v dd supply power supply: voltage dependant on option. a1, e3, j1 v ss supply ground.
128mb: x16, x32 mobile sdram 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobile_2.fm - rev. g (draft) 7/04 en 10 ?2001 micron technology, inc. all rights reserved. table 4: ball descriptions: 90-ball vfbga 90-ball fbga symbol type description j1 clk input clock: clk is driven by the system clock. all sdram input signals are sampled on the positive edge of clk. clk also increments the internal burst counter and controls the output registers. j2 cke input clock enable: cke activates (high) and deactivates (low) the clk signal. deactivating the clock provides precharge power-down and self refresh operation (all banks idle), active power-down (row active in any bank) or clock suspend operation (burst/access in progress). cke is synchronous except after the device enters power-down and self refresh modes, where cke becomes asynchro nous until after exiting the same mode. the input buffers, including clk, are disabled during power-down and self refresh modes, providing low standby power. cke may be tied high. j8 cs# input chip select: cs# enables (registered low) and disables (registered high) the command decoder. all commands are masked when cs# is registered high. cs# provides for external bank selection on systems with multiple banks. cs# is considered part of the command code. j9, k7, k8 ras#, cas#, we# input command inputs: ras#, cas#, and we# (along with cs#) define the command being entered. k9, k1, f8, f2 dqm0?3 input input/output mask: dqm is sampled high and is an input mask signal for write accesses and an output enable signal for read accesses. input data is masked during a write cycle. the output buffers are placed in a high-z state (two-clock latency) when during a read cycle. dqm0 corresponds to dq0?dq7, dqm1 corresponds to dq8?dq15, dqm2 corresponds to dq16?dq23 and dqm3 corresponds to dq24?dq31. dqm0-3 are considered same state when referenced as dqm. j7, h8 ba0, ba1 input bank address input(s): ba0 and ba1 define to which bank the active, read, write or precharge command is being applied. these pins also provide the op-code during a load mode register command g8, g9, f7, f3, g1, g2, g3, h1, h2, j3, g7, h9 a0?a5 a6-a11 input address inputs: a0?a11 are sampled during the active command (row- address a0?a11) and read/write command (column-address a0?a7; with a10 defining auto precharge) to select one location out of the memory array in the respective bank. a10 is sampled during a precharge command to determine if all banks are to be precharged (a10 high) or bank selected by ba0, ba1 (low). the address inputs also provide the op-code during a load mode register command. r8, n7, r9, n8, p9, m8, m7, l8, l2, m3, m2, p1, n2, r1, n3, r2, e8, d7, d8, b9, c8, a9, c7, a8, a2, c3, a1, c2, b1, d2, d3, e2 dq0?dq5 dq6-dq11 dq12-dq17 dq18-dq23 dq24-dq29 dq30-dq31 i/o data input/output: data bus e3, e7, h3, h7, k2, k3 nc ? no connect: these pins should be left unconnected. h3 is a no connect for this part but may be used as a12 in future designs. b2, b7, c9, d9, e1, l1, m9, n9, p2, p7 v dd q supply dq power: isolated dq power on the die to improve noise immunity. b8, b3, c1, d1, e9, l9, m1, n1, p3, p8 v ss q supply dq ground: isolated dq power on the die to improve noise immunity. a7, f9, l7, r7 v dd supply power supply: voltage dependant on option. a3, f1, l3, r3 v ss supply ground.
128mb: x16, x32 mobile sdram 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobile_2.fm - rev. g (draft) 7/04 en 11 ?2001 micron technology, inc. all rights reserved. table 5: pin descriptions: 54-pin tsop (x16 only) tsop pin number symbol type description 38 clk input clock: clk is driven by the system clock. all sdram input signals are sampled on the positive edge of clk. clk also increments the internal burst counter and controls the output registers. 37 cke input clock enable: cke activates (high) and deactivates (low) the clk signal. deactivating the clock provides precharge power-down and self refresh operation (all banks idle), active power-down (row active in any bank) or clock suspend operation (burst/access in progress). cke is synchronous except after the device enters power-down and self refresh modes, where cke becomes asynchro nous until after exiting the same mode. the input buffers, including clk, are disabled during power-down and self refresh modes, providing low standby power. cke may be tied high. 19 cs# input chip select: cs# enables (registered low) and disables (registered high) the command decoder. all commands are masked when cs# is registered high. cs# provides for external bank selection on systems with multiple banks. cs# is considered part of the command code. 16, 17, 18 we#, cas#, ras# input command inputs: we#, cas#, and ras# (along with cs#) define the command being entered. 15, 39 dqml, dqmh input input/output mask: dqm is sampled high and is an input mask signal for write accesses and an output enable signal for read accesses. input data is masked during a write cycle. the output buffers are placed in a high-z state (two-clock latency) when during a read cycle. dqm0 corresponds to dq0?dq7, dqm1 corresponds to dq8?dq15, dqm2 corresponds to dq16?dq23 and dqm3 corresponds to dq24?dq31. ldqm corresponds to dq0?dq7, udqm corresponds to dq8?dq15. ldqm and udqm are considered same state when referenced as dqm. 20, 21 ba0, ba1 input bank address input(s): ba0 and ba1 define to which bank the active, read, write or precharge command is being applied. these pins also provide the op-code during a load mode register command 23, 24, 25, 29, 30, 31, 32, 33, 34, 22, 35 a0?a5 a6-a11 input address inputs: a0?a11 are sampled during the active command (row- address a0?a11) and read/write command (column-address a0?a7; with a10 defining auto precharge) to select one location out of the memory array in the respective bank. a10 is sampled during a precharge command to determine if all banks are to be precharged (a10 high) or bank selected by ba0, ba1 (low). the address inputs also provide the op-code during a load mode register command. 2, 4, 5, 7, 8, 10, 11, 13, 42, 49,45, 47, 48, 50, 51 dq0?dq7 dq8-dq15 i/o data input/output: data bus (x16 only) 36, 40 nc ? no connect: these pins should be left unconnected. pin 36 is a no connect for this part but may be used as a12 in future designs. 3, 9, 43, 49 v dd q supply dq power: isolated dq power on the die to improve noise immunity. 6, 12, 46, 52 v ss q supply dq ground: isolated dq power on the die to improve noise immunity. 1, 14, 27 v dd supply power supply: voltage dependant on option. 28, 41, 54 v ss supply ground.
128mb: x16, x32 mobile sdram 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobile_2.fm - rev. g (draft) 7/04 en 12 ?2001 micron technology, inc. all rights reserved. functional description in general, the 128mb sdrams (2 meg x16 x 4 banks and 1 meg x 32 x 4 banks) are quad-bank drams that operate at 3.3v or 2.5v and include a synchronous interface (all signals are registered on the positive edge of the clock signal, clk). each of the x16?s 33,554,432- bit banks is organized as 4,096 rows by 512 columns by 16 bits. each of the x32?s 33,554,432-bit banks is orga- nized as 4,096 rows by 256 columns by 32bits. read and write accesses to the sdram are burst ori- ented; accesses start at a selected location and con- tinue for a programmed number of locations in a programmed sequence. accesses begin with the regis- tration of an active command, which is then fol- lowed by a read or write command. the address bits registered coincident with the active command are used to select the bank and row to be accessed (ba0 and ba1 select the bank, a0-a11 select the row). the address bits (x16: a0-a8; x32: a0-a7) registered coincident with the read or write command are used to select the starting column location for the burst access. prior to normal operation, the sdram must be ini- tialized. the following sections provide detailed infor- mation covering device initialization, register definition, command descriptions and device opera- tion. initialization sdrams must be powered up and initialized in a predefined manner. operational procedures other than those specified may result in undefined opera- tion. once power is applied to vdd and vddq (simulta- neously) and the clock is stable (stable clock is defined as a signal cycling within timing constraints specified for the clock pin), the sdram requires a 100s delay prior to issuing any command other than a com- mand inhibit or nop. starting at some point during this 100s period and continuing at least through the end of this period, command inhibit or nop com- mands should be applied. once the 100s delay has been satisfied with at least one command inhibit or nop command having been applied, a precharge command should be applied. all banks must then be precharged, thereby placing the device in the all banks idle state. once in the idle state, two auto refresh cycles must be performed. after the auto refresh cycles are com- plete, the sdram is ready for mode register program- ming. because the mode register will power up in an unknown state, it should be loaded prior to applying any operational command. register definition mode register in order to achieve low power consumption, there are two mode registers in the mobile component, mode register and extended mode register. for this section, mode register is referred to. extended mode register is discussed on 15 . the mode register is used to define the specific mode of operation of the sdram. this definition includes the selection of a burst length, a burst type, a cas latency, an operating mode and a write burst mode, as shown in figure 7. the mode reg- ister is programmed via the load mode register command and will retain the stored information until it is programmed again or the device loses power. mode register bits m0-m2 specify the burst length, m3 specifies the type of burst (sequential or inter- leaved), m4-m6 specify the cas latency, m7 and m8 specify the operating mode, m9 specify the write burst mode (single or programmed burst length), m10, and m11 are reserved and must be set to zero. to address the mode register m12 and m13 must be set to zero. the mode register must be loaded when all banks are idle, and the controller must wait the specified time before initiating the subsequent operation. vio- lating either of these requirements will result in unspecified operation. burst length read and write accesses to the sdram are burst ori- ented, with the burst length being programmable, as shown in figure 8 on page 14. the burst length deter- mines the maximum number of column locations that can be accessed for a given read or write command. burst lengths of 1, 2, 4, or 8 locations are available for both the sequential and the interleaved burst types, and a full-page burst is available for the sequential type. the full-page burst is used in conjunction with the burst terminate command to generate arbi- trary burst lengths. if a full page burst is not termi- nated at the end of the page it could wrap to column zero and continue. reserved states should not be used, as unknown operation or incompatibility with future versions may result. when a read or write command is issued, a block of columns equal to the burst length is effectively selected. all accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is reached. the block is uniquely selected by a1-a8 (x16) or a1-a7 (x32) when the burst
128mb: x16, x32 mobile sdram 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobile_2.fm - rev. g (draft) 7/04 en 13 ?2001 micron technology, inc. all rights reserved. length is set to two; by a2-a8 (x16) or a2-a7 (x32) when the burst length is set to four; and by a3-a8 (x16) or a3- a7 (x32) when the burst length is set to eight. the remaining (least significant) address bit(s) is (are) used to select the starting location within the block. full- page bursts wrap within the page if the boundary is reached. burst type accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit m3. note only a sequential burst is allowed for full page bursts. the ordering of accesses within a burst is deter- mined by the burst length, the burst type and the start- ing column address, as shown in table 6 on page 14. figure 7: mode register definition 10 m3 = 0 1 2 4 8 reserved reserved reserved full page m3 = 1 1 2 4 8 reserved reserved reserved reserved operating mode standard operation all other states reserved 0 - 0 - valid - 0 1 burst type sequential interleaved cas latency reserved 1 2 3 reserved reserved reserved reserved burst length m0 0 1 0 1 0 1 0 1 burst length cas latency bt a9 a7 a6 a5 a4 a3 a8 a2 a1 a0 mode register (mx) address bus 9 7 654 3 8 2 1 0 m1 0 0 1 1 0 0 1 1 m2 0 0 0 0 1 1 1 1 m3 m4 0 1 0 1 0 1 0 1 m5 0 0 1 1 0 0 1 1 m6 0 0 0 0 1 1 1 1 m6-m0 m8 m7 op mode a10 reserved wb 0 1 write burst mode programmed burst length single location access m9 ba0 ba1 m9 m7 m6 m5 m4 m3 m8 m2 m1 m0 m10 11 a11 m11 m12 m13 mr 13 12 mode register definition program mode register program extended mode register 0 1 0 0 m13 m12 valid - m9 0 - m10 0 - m11
128mb: x16, x32 mobile sdram 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobile_2.fm - rev. g (draft) 7/04 en 14 ?2001 micron technology, inc. all rights reserved. note: 1. for full-page accesses: y = 512 (x16), y = 256 (x32). 2. for a burst length of two, a1-a8 (x16) or a1-a7 (x32) select the block-of-two burst; a0 selects the starting column within the block. 3. for a burst length of four, a2-a8 (x16) or a2-a7 (x32) select the block-of-four burst; a0-a1 select the starting column within the block. 4. for a burst length of eight, a3-a8 (x16) or a3-a7 (x32) select the block-of-eight burst; a0-a2 select the start- ing column within the block. 5. for a full-page burst, the full row is selected and a0-a8 (x16) or a0-a7 (x32) select the starting column. 6. whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block. 7. for a burst length of one, a0-a8 (x16) or a0-a7 (x32) select the unique column to be accessed, and mode register bit m3 is ignored. cas latency the cas latency is the delay, in clock cycles, between the registration of a read command and the availability of the first piece of output data. the latency can be set to one, two, or three clocks. if a read command is registered at clock edge n , and the latency is m clocks, the data will be available by clock edge n + m . the dqs will start driving as a result of the clock edge one cycle earlier ( n + m - 1), and provided that the relevant access times are met, the data will be valid by clock edge n + m . for example, assuming that the clock cycle time is such that all rele- vant access times are met, if a read command is regis- tered at t0 and the latency is programmed to two clocks, the dqs will start driving after t1 and the data will be valid by t2, as shown in figure 8. table 7 indi- cates the operating frequencies at which each cas latency setting can be used. reserved states should not be used as unknown operation or incompatibility with future versions may result. figure 8: cas latency table 6: burst definition burst length starting column address order of accesses within a burst ty pe = sequential ty pe = interleaved 2a0 00-1 0-1 11-0 1-0 4a1a0 0 0 0-1-2-3 0-1-2-3 0 1 1-2-3-0 1-0-3-2 1 0 2-3-0-1 2-3-0-1 1 1 3-0-1-2 3-2-1-0 8a2a1a0 0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3 1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2 1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1 1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0 full page (y) n = a0-a8 for x16, a0-a7 for x32 (location 0-y) cn, cn + 1, cn + 2 cn + 3, cn + 4... ?cn - 1, cn? not supported clk dq t2 t1 t3 t0 cas latency = 3 lz d out t oh t command nop read t ac nop t4 nop don?t care undefined clk dq t2 t1 t0 cas latency = 1 lz d out t oh t command nop read t ac clk dq t2 t1 t3 t0 cas latency = 2 lz d out t oh t command nop read t ac nop
128mb: x16, x32 mobile sdram 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobile_2.fm - rev. g (draft) 7/04 en 15 ?2001 micron technology, inc. all rights reserved. write burst mode when m9=0, the burst length programmed into m0- m2 applies to both read and write burst. if m9 = 1, all write bursts will only be single location access regardless of the burst length setting in the mode regis- ter. read burst lengths are unaffected by the state of m9. operating mode the normal operating mode is selected by setting m7, m8, m10 and m11 to zero; all the other combina- tions of values for m7, m8, m10 and m11 are reserved for future use and/or test modes. test modes and reserved states should not be used because unknown operation or incompatibility with future versions may result. extended mode register the extended mode register controls the functions beyond those controlled by the mode register. these additional functions are special features of the mobile device. they include temperature compensated self refresh control (tcsr), and partial array self refresh (pasr). figure 9: extende d mode register the extended mode register is programmed via the mode register set command (ba1=1,ba0=0) and retains the stored information until it is programmed again or the device loses power. the extended mode register must be programmed with e5 through e11 set to ?0?. the extended mode register must be loaded when all banks are idle and no bursts are in progress, and the controller must wait the specified time before initiating any subsequent opera- tion. violating either of these requirements results in unspecified operation. the extended mode register must be programmed in order to ensure proper opera- tion. temperature compensated self refresh temperature compensated self refresh (tcsr) allows the controller to program the refresh interval during self refresh mode, according to the case temperature of the mobile device. this allows great power savings during self refresh during most operating temperature ranges. only during extreme table 7: cas latency speed allowable operating frequency (mhz) cas latency = 1 cas latency = 2 cas latency = 3 -75m - 100 133 - 8 50 100 125 - 10 40 83 100 address bus 976543 821 pasr tcsr set to "0" emr e13 e12 a11 e11 a10 e10 a9 e9 a8 e8 a7 e7 a6 e6 a5 e5 a4 e4 a3 e3 a2 e2 a1 e1 a0 e0 10 11 12 13 notes: 1. m13 and m12 (ba1 and ba0) must be ?1, 0? to select the extended mode register (vs. the base mode register). 2. rfu: reserved for future use partial array self refresh coverage fullarray (all banks) half array (ba1 = 0) quarter array (ba1 = ba0 = 0) rfu rfu rfu rfu rfu ba1 ba0 0 0 1 1 mode register definintion mode register reserved extended mode registe r resereved m13 0 1 0 1 m12 0 e11 e10 e9 e8 e7 e6 e5 e4 e3 e2 e1 e0 operating mode 0 - 0 - 0 - 0 - 0 - valid - normal operation all other states reserved extended mode register (ex) 0 - 0 - e2 0 0 0 0 1 1 1 1 e1 0 0 1 1 0 0 1 1 e0 0 1 0 1 0 1 0 1 maximum case temp 85?c 70?c 45?c 15?c e4 1 0 0 1 e3 1 0 1 0
128mb: x16, x32 mobile sdram 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobile_2.fm - rev. g (draft) 7/04 en 16 ?2001 micron technology, inc. all rights reserved. temperatures would the controller have to select a higher tcsr level that will guarantee data during self refresh. every cell in the dram requires refreshing due to the capacitor losing its charge over time. the refresh rate is dependent on temperature. at higher tempera- tures a capacitor loses charge quicker than at lower temperatures, requiring the cells to be refreshed more often. historically, during self refresh, the refresh rate has been set to accommodate the worst case, or high- est temperature range expected. thus, during ambient temperatures, the power con- sumed during refresh was unnecessarily high, because the refresh rate was set to accommodate the higher temperatures. setting e4 and e3, allows the dram to accommodate more specific temperature regions dur- ing self refresh. there are four temperature set- tings, which will vary the self refresh current according to the selected temperature. this selectable refresh rate will save power when the dram is operat- ing at normal temperatures. partial array self refresh for further power savings during self refresh, the partial array self refresh (pasr) feature allows the controller to select the amount of memory that will be refreshed during self refresh. the refresh options are all banks (banks 0, 1, 2, and 3); two banks (banks 0 and 1); and one bank (bank 0). write and read com- mands occur to any bank selected during standard operation, but only the selected banks in pasr will be refreshed during self refresh. it?s important to note that data in banks 2 and 3 will be lost when the two bank option is used. data will be lost in banks 1, 2, and 3 when the one bank option is used.
128mb: x16, x32 mobile sdram 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobile_2.fm - rev. g (draft) 7/04 en 17 ?2001 micron technology, inc. all rights reserved. commands truth table 1 provides a quick reference of available commands. this is followed by a written description of each command. three additional truth tables appear following the operation section; these tables provide current state/next state information. note: 1. cke is high for all commands shown except self refresh. 2. a0-a10 define the op-code written to the mode register. ba0- ba1 select either the mode register or the extended mode register (ba0=ba1=0 select the mode register, ba1=1, ba0=0 selects the extended mode register, all other combinations of ba0-ba1 are reserved.) 3. a0-a11 provide row address, and ba0, ba1 determine which bank is made active. 4. a0-a8 (x16) or a0-a7 (x32) provide column address; a10 high enables the auto precharge feature (nonpersistent), while a10 low disables the auto precharge feature; ba0, ba1 determine which bank is being read from or written to. 5. a10 low: ba0, ba1 determine the bank being precharged . a10 high: all banks precharged and ba0, ba1 are ?don?t care.? 6. this command is auto refresh if cke is high, self refresh if cke is low. 7. internal refresh counter controls row addressing; all inputs and i/os are ?don?t care? except for cke. 8. activates or deactivates the dqs during writes (zero-clock de lay) and reads (two-clock delay).for x16: ldqm controls dq0-dq7 and udqm controls dq8-dq15. for x32: dqm0 contro ls dq0-7, dqm1 controls dq8-15, dqm2 controls dq16- 23, and dqm3 controls dq24-31. table 8: truth table?commands and dqm operation (note: 1) name (function) cs# ras# cas# we# dqm addr dqs notes command inhibit (nop) hx x x x x x no operation (nop) lhhhx x x active (select bank and activate row) l l h h x bank/row x 3 read (select bank and column, and start read burst) lh l h l/h 8 bank/col x 4 write (select bank and column, and start write burst) lh l l l/h 8 bank/col valid 4 burst terminate lhh l x x active precharge (deactivate row in bank or banks) llhlx code x 5 auto refresh or self refresh (enter self refresh mode) ll lhx x x 6, 7 load mode register l l l l x op-code x 2 write enable/output enable ?? ? ? l ? active8 write inhibit/output high-z ? ? ? ? h ? high-z 8
128mb: x16, x32 mobile sdram 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobile_2.fm - rev. g (draft) 7/04 en 18 ?2001 micron technology, inc. all rights reserved. command inhibit the command inhibit function prevents new commands from being executed by the sdram, regardless of whether the clk signal is enabled. the sdram is effectively deselected. operations already in progress are not affected. no operation (nop) the no operation (nop) command is used to instruct the selected sdram to perform a nop (ras#, cas#, and we# are high, cs# is low). this prevents unwanted commands from being registered during idle or wait states. operations already in progress are not affected. load mode register the mode register is loaded via inputs a0?a11. refer to ?mode register definition? on page 13. the load mode register and load extended mode reg- ister commands can only be issued when all banks are idle, and a subsequent executable command can- not be issued until t mrd is met. active the active command is used to open (or activate) a row in a particular bank for a subsequent access. the value on the ba0, ba1 inputs selects the bank, and the address provided on inputs a0-a11 selects the row. this row remains active (or open) for accesses until a precharge command is issued to that bank. a pre- charge command must be issued before opening a different row in the same bank. read the read command is used to initiate a burst read access to an active row. the value on the ba0, ba1 inputs selects the bank, and the address provided on inputs a0-a8 (x16) or a0-a7 (x32) selects the starting column location. the value on input a10 determines whether or not auto precharge is used. if auto pre- charge is selected, the row being accessed will be pre- charged at the end of the read burst; if auto precharge is not selected, the row will remain open for subse- quent accesses. read data appears on the dqs subject to the logic level on the dqm inputs two clocks earlier. if a given dqm signal was registered high, the corre- sponding dqs will be high-z two clocks later; if the dqm signal was registered low, the dqs will provide valid data. write the write command is used to initiate a burst write access to an active row. the value on the ba0, ba1 inputs selects the bank, and the address provided on inputs a0-a8 (x16) or a0-a7 (x32) selects the start- ing column location. the value on input a10 deter- mines whether or not auto precharge is used. if auto precharge is selected, the row being accessed will be precharged at the end of the write burst; if auto pre- charge is not selected, the row will remain open for subsequent accesses. input data appearing on the dqs is written to the memory array subject to the dqm input logic level appearing coincident with the data. if a given dqm signal is registered low, the correspond- ing data will be written to memory; if the dqm signal is registered high, the corresponding data inputs will be ignored, and a write will not be executed to that byte/column location. precharge the precharge command is used to deactivate the open row in a particular bank or the open row in all banks. the bank(s) will be available for a subsequent row access a specified time ( t rp) after the precharge command is issued. input a10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs ba0, ba1 select the bank. otherwise ba0, ba1 are treated as ?don?t care.? once a bank has been precharged, it is in the idle state and must be activated prior to any read or write commands being issued to that bank. auto precharge auto precharge is a feature which performs the same individual-bank precharge function described above, without requiring an explicit command. this is accomplished by using a10 to enable auto precharge in conjunction with a specific read or write com- mand. a precharge of the bank/row that is addressed with the read or write command is automatically performed upon completion of the read or write burst, except in the full-page burst mode, where auto precharge does not apply. auto precharge is non per- sistent in that it is either enabled or disabled for each individual read or write command. auto precharge ensures that the precharge is initi- ated at the earliest valid stage within a burst. the user must not issue another command to the same bank until the precharge time ( t rp) is completed. this is determined as if an explicit precharge command was issued at the earliest possible time, as described for each burst type in the operation section of this data sheet.
128mb: x16, x32 mobile sdram 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobile_2.fm - rev. g (draft) 7/04 en 19 ?2001 micron technology, inc. all rights reserved. burst terminate the burst terminate command is used to trun- cate either fixed-length or full-page bursts. the most recently registered read or write command prior to the burst terminate command will be truncated, as shown in the operation section of this data sheet. auto refresh auto refresh is used during normal operation of the sdram and is analogous to cas#-before-ras# (cbr) refresh in conventional drams. this command is nonpersistent, so it must be issued each time a refresh is required. all active banks must be pre- charged prior to issuing an auto refresh com- mand. the auto refresh command should not be issued until the minimum t rp has been met after the precharge command as shown in the operation sec- tion. the addressing is generated by the internal refresh controller. this makes the address bits ?don?t care? during an auto refresh command. the 128mb sdram requires 4,096 auto refresh cycles every 64ms ( t ref), regardless of width option. providing a distributed auto refresh command every 15.625s will meet the refresh requirement and ensure that each row is refreshed. alternatively, 4,096 auto refresh commands can be issued in a burst at the minimum cycle rate ( t rfc), once every 64ms. self refresh the self refresh command can be used to retain data in the sdram, even if the rest of the system is powered down. when in the self refresh mode, the sdram retains data without external clocking. the self refresh command is initiated like an auto refresh command except cke is disabled (low). once the self refresh command is registered, all the inputs to the sdram become ?don?t care? with the exception of cke, which must remain low. once self refresh mode is engaged, the sdram pro- vides its own internal clocking, causing it to perform its own auto refresh cycles. the sdram must remain in self refresh mode for a minimum period equal to t ras and may remain in self refresh mode for an indef- inite period beyond that. the procedure for exiting self refresh requires a sequence of commands. first, clk must be stable (sta- ble clock is defined as a signal cycling within timing constraints specified for the clock pin) prior to cke going back high. once cke is high, the sdram must have nop commands issued (a minimum of two clocks, regardless of clock frequency) for t xsr because time is required for the completion of any internal refresh in progress. upon exiting the self refresh mode, auto refresh commands must be issued every 15.625s or less as both self refresh and auto refresh utilize the row refresh counter.
128mb: x16, x32 mobile sdram 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobile_2.fm - rev. g (draft) 7/04 en 20 ?2001 micron technology, inc. all rights reserved. operation bank/row activation before any read or write commands can be issued to a bank within the sdram, a row in that bank must be ?opened.? this is accomplished via the active command, which selects both the bank and the row to be activated (seefigure 10). after opening a row (issuing an active command), a read or write command may be issued to that row, subject to the t rcd specification. t rcd (min) should be divided by the clock period and rounded up to the next whole number to determine the earliest clock edge after the active command on which a read or write command can be entered. for example, a t rcd specification of 20ns with a 125 mhz clock (8ns period) results in 2.5 clocks, rounded to 3. this is reflected in figure 11, which covers any case where 2 < t rcd (min)/ t ck 3. (the same procedure is used to convert other specification limits from time units to clock cycles.) a subsequent active command to a different row in the same bank can only be issued after the previous active row has been ?closed? (precharged). the mini- mum time interval between successive active com- mands to the same bank is defined by t rc. a subsequent active command to another bank can be issued while the first bank is being accessed, which results in a reduction of total row-access over- head. the minimum time interval between successive active commands to different banks is defined by t rrd. figure 10: activating a specific row in a specific bank figure 11: example: meeting t rcd (min) when 2 < t rcd (min)/ t ck< 3 cs# we# cas# ras# cke clk a0?a10, a11 row address don?t care high ba0, ba1 bank address clk t2 t1 t3 t0 t command nop active read or write t4 nop rcd don?t care
128mb: x16, x32 mobile sdram 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobile_2.fm - rev. g (draft) 7/04 en 21 ?2001 micron technology, inc. all rights reserved. reads read bursts are initiated with a read command, as shown in figure 12. the starting column and bank addresses are pro- vided with the read command, and auto precharge is either enabled or disabled for that burst access. if auto precharge is enabled, the row being accessed is pre- charged at the completion of the burst. for the read commands used in the following illustrations, auto precharge is disabled. during read bursts, the valid data-out element from the starting column address will be available fol- lowing the cas latency after the read command. each subsequent data-out element will be valid by the next positive clock edge. figure 13 shows general tim- ing for each possible cas latency setting. figure 12: read command upon completion of a burst, assuming no other commands have been initiated, the dqs will go high- z. a full-page burst will continue until terminated. (at the end of the page, it will wrap to column 0 and con- tinue.) data from any read burst may be truncated with a subsequent read command, and data from a fixed- length read burst may be immediately followed by data from a read command. in either case, a continu- ous flow of data can be maintained. the first data ele- ment from the new burst follows either the last element of a completed burst or the last desired data element of a longer burst that is being truncated. the new read command should be issued x cycles before the clock edge at which the last desired data element is valid, where x equals the cas latency minus one. figure 13: cas latency don?t care cs# we# cas# ras# cke clk column address x16: a0-a8 x32: a0-a7 a10 ba0,1 high enable auto precharge disable auto precharge bank address a9, a11 clk dq t2 t1 t3 t0 cas latency = 3 lz d out t oh t command nop read t ac nop t4 nop don?t care undefined clk dq t2 t1 t0 cas latency = 1 lz d out t oh t command nop read t ac clk dq t2 t1 t3 t0 cas latency = 2 lz d out t oh t command nop read t ac nop
128mb: x16, x32 mobile sdram 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobile_2.fm - rev. g (draft) 7/04 en 22 ?2001 micron technology, inc. all rights reserved. this is shown in figure 14 for cas latencies of two and three; data element n + 3 is either the last of a burst of four or the last desired of a longer burst. the 128mb sdram uses a pipelined architecture and therefore does not require the 2 n rule associated with a prefetch architecture. a read command can be initiated on any clock cycle following a previous read command. full-speed random read accesses can be performed to the same bank, as shown in figure 15, or each subse- quent read may be performed to a different bank. figure 14: consecutive read bursts clk dq d out n t2 t1 t4 t3 t5 t0 command address read nop nop nop bank, col n nop bank, col b d out n + 1 d out n + 2 d out n + 3 d out b read x = 0 cycles note: each read command may be to either bank. dqm is low. shown with bl=4. cas latency = 1 clk dq d out n t2 t1 t4 t3 t6 t5 t0 command address read nop nop nop nop bank, col n nop bank, col b d out n + 1 d out n + 2 d out n + 3 d out b read x = 1 cycle cas latency = 2 clk dq d out n t2 t1 t4 t3 t6 t5 t0 command address read nop nop nop nop bank, col n nop bank, col b d out n + 1 d out n + 2 d out n + 3 d out b read nop t7 x = 2 cycles cas latency = 3 don?t care transitioning data
128mb: x16, x32 mobile sdram 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobile_2.fm - rev. g (draft) 7/04 en 23 ?2001 micron technology, inc. all rights reserved. figure 15: random read accesses clk dq t2 t1 t4 t3 t6 t5 t0 command address read nop nop bank, col n don?t care d out n d out a d out x d out m read notes: 1) each read command may be to either bank. dqm is low. read read nop bank, col a bank, col x bank, col m clk dq d out n t2 t1 t4 t3 t5 t0 command address read nop bank, col n d out a d out x d out m read read read nop bank, col a bank, col x bank, col m clk dq d out n t2 t1 t4 t3 t0 command address read nop bank, col n d out a d out x d out m readreadread bank, col a bank, col x bank, col m cas latency = 1 cas latency = 2 cas latency = 3 transitioning data 2) burst length = 1, 2, 4, 8 or full page (if bl > 1 the following read interrupts the previous)
128mb: x16, x32 mobile sdram 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobile_2.fm - rev. g (draft) 7/04 en 24 ?2001 micron technology, inc. all rights reserved. data from any read burst may be truncated with a subsequent write command, and data from a fixed- length read burst may be immediately followed by data from a write command (subject to bus turn- around limitations). the write burst may be initiated on the clock edge immediately following the last (or last desired) data element from the read burst, pro- vided that i/o contention can be avoided. in a given system design, there may be a possibility that the device driving the input data will go low-z before the sdram dqs go high-z. in this case, at least a single- cycle delay should occur between the last read data and the write command. figure 16: read to write the dqm input is used to avoid i/o contention, as shown in figure 16 and figure 17. the dqm signal must be asserted (high) at least two clocks prior to the write command (dqm latency is two clocks for output buffers) to suppress data-out from the read. once the write command is registered, the dqs will go high-z (or remain high-z), regardless of the state of the dqm signal, provided the dqm was active on the clock just prior to the write command that truncated the read command. if not, the second write will be an invalid write. for example, if dqm was low dur- ing t4 in figure17, then the writes at t5 and t7 would be valid, while the write at t6 would be invalid. the dqm signal must be de-asserted prior to the write command (dqm latency is zero clocks for input buffers) to ensure that the written data is not masked. figure 16 shows the case where the clock fre- quency allows for bus contention to be avoided with- out adding a nop cycle, and figure 17 shows the case where the additional nop is needed. figure 17: read to write with extra clock cycle a fixed-length read burst may be followed by, or truncated with, a precharge command to the same bank (provided that auto precharge was not activated), and a full-page burst may be truncated with a pre- charge command to the same bank. the pre- charge command should be issued x cycles before the clock edge at which the last desired data element is valid, where x equals the cas latency minus one. this is shown in figure 18 for each possible cas latency; data element n + 3 is either the last of a burst of four or the last desired of a longer burst. following the pre- charge command, a subsequent command to the same bank cannot be issued until t rp is met. note that part of the row precharge time is hidden during the access of the last data element(s). in the case of a fixed-length burst being executed to completion, a precharge command issued at the optimum time (as described above) provides the same operation that would result from the same fixed-length burst with auto precharge. the disadvantage of the precharge command is that it requires that the command and address buses be available at the appropriate time to issue the command; the advantage of the precharge command is that it can be used to truncate fixed-length or full-page bursts. don?t care read nop nop write nop clk t2 t1 t4 t3 t0 dqm dq d out n command d in b address bank, col n bank, col b ds t hz t t ck notes: 1) a cas latency of three is used for illustration. 2) the read command may be to any bank, and the write command may be to any bank. 3) if a burst of one is used, then dqm is not required. transitioning data don?t care read nop nop nop nop dqm clk dq d out n t2 t1 t4 t3 t0 command address bank, col n write d in b bank, col b t5 ds t hz t note: a cas latency of three is used for illustration. the read command may be to any bank, and the write command may be to any bank. transitioning data
128mb: x16, x32 mobile sdram 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobile_2.fm - rev. g (draft) 7/04 en 25 ?2001 micron technology, inc. all rights reserved. figure 18: read to precharge clk dq d out n t2 t1 t4 t3 t6 t5 t0 command address read nop nop nop nop nop d out n + 1 d out n + 2 d out n + 3 precharge active t rp t7 clk dq d out n t2 t1 t4 t3 t6 t5 t0 command address read nop nop nop nop nop d out n + 1 d out n + 2 d out n + 3 precharge active t rp t7 clk dq d out n t2 t1 t4 t3 t6 t5 t0 command address read nop nop nop nop bank a , col n nop d out n + 1 d out n + 2 d out n + 3 precharge active t rp t7 bank a , row bank ( a or all) don?t care x = 0 cycles cas latency = 1 x = 1 cycle cas latency = 2 cas latency = 3 bank a , col n bank a , row bank ( a or all) bank a , col n bank a , row bank ( a or all) x = 2 cycles transitioning data notes: 1) assumes tras(min) has been satisfied prior to the precharge command 2) n+3 is either the last data element of a bl=4, or the last desired data element of a longer burst 3) dqm is low.
128mb: x16, x32 mobile sdram 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobile_2.fm - rev. g (draft) 7/04 en 26 ?2001 micron technology, inc. all rights reserved. full-page read bursts can be truncated with the burst terminate command, and fixed-length read bursts may be truncated with a burst termi- nate command, provided that auto precharge was not activated. the burst terminate command should be issued x cycles before the clock edge at which the last desired data element is valid, where x equals the cas latency minus one. this is shown in figure 19 for each possible cas latency; data element n + 3 is the last desired data element of a longer burst. figure 19: terminating a read burst don?t care clk dq d out n t2 t1 t4 t3 t6 t5 t0 command address read nop nop nop nop bank, col n nop d out n + 1 d out n + 2 d out n + 3 burst terminate nop t7 clk dq d out n t2 t1 t4 t3 t6 t5 t0 command address read nop nop nop bank, col n nop d out n + 1 d out n + 2 d out n + 3 burst terminate nop clk dq d out n t2 t1 t4 t3 t6 t5 t0 command address read nop nop nop bank, col n nop d out n + 1 d out n + 2 d out n + 3 burst terminate nop x = 0 cycles cas latency = 1 x = 1 cycle cas latency = 2 cas latency = 3 x = 2 cycles transitioning data notes: 1) page remains open after a burst terminate command 2) n+3 is either the last data element of a burst of four, or the last desired dta element of a longer burst. 3) dqm is low.
128mb: x16, x32 mobile sdram 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobile_2.fm - rev. g (draft) 7/04 en 27 ?2001 micron technology, inc. all rights reserved. writes write bursts are initiated with a write command, as shown in figure 20. the starting column and bank addresses are pro- vided with the write command, and auto precharge is either enabled or disabled for that access. if auto precharge is enabled, the row being accessed is pre- charged at the completion of the burst. for the write commands used in the following illustrations, auto precharge is disabled. during write bursts, the first valid data-in element will be registered coincident with the write com- mand. subsequent data elements will be registered on each successive positive clock edge. upon completion of a fixed-length burst, assuming no other commands have been initiated, the dqs will remain high-z and any additional input data will be ignored (see figure 21). a full-page burst will continue until termi- nated. (at the end of the page, it will wrap to column 0 and continue.) figure 20: write command data for any write burst may be truncated with a subsequent write command, and data for a fixed- length write burst may be immediately followed by data for a write command. the new write com- mand can be issued on any clock following the previ- ous write command, and the data provided coincident with the new command applies to the new command. an example is shown in figure 21. data n + 1 is either the last of a burst of two or the last desired of a longer burst. the 128mb sdram uses a pipelined architecture and therefore does not require the 2n rule associated with a prefetch architecture. a write com- mand can be initiated on any clock cycle following a previous write command. full-speed random write accesses within a page can be performed to the same bank, as shown in figure 22, or each subsequent write may be performed to a different bank. figure 21: write burst figure 22: write to write data for any write burst may be truncated with a subsequent read command, and data for a fixed- length write burst may be immediately followed by a read command. once the read command is regis- tered, the data inputs will be ignored, and writes will cs# we# cas# ras# cke clk column address don?t care high enable auto precharge disable auto precharge bank address x16: a0-a8 x32: a0-a7 a10 ba0,1 a9, a11 valid address clk dq d in n t2 t1 t3 t0 command address nop nop write d in n + 1 nop bank, col n note: burst length = 2. dqm is low. don?t care transitioning data don?t care clk dq t2 t1 t0 command address nop write write bank, col n bank, col b d in n d in n + 1 d in b note: dqm is low. each write command may be to any bank. transitioning data
128mb: x16, x32 mobile sdram 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobile_2.fm - rev. g (draft) 7/04 en 28 ?2001 micron technology, inc. all rights reserved. not be executed. an example is shown in figure 24. data n + 1 is either the last of a burst of two or the last desired of a longer burst. data for a fixed-length write burst may be fol- lowed by, or truncated with, a precharge command to the same bank (provided that auto precharge was not activated), and a full-page write burst may be truncated with a precharge command to the same bank. the precharge command should be issued t wr after the clock edge at which the last desired input data element is registered. the auto precharge mode requires a t wr of at least one clock plus time, regard- less of frequency. in addition, when truncating a write burst, the dqm signal must be used to mask input data for the clock edge prior to, and the clock edge coincident with, the precharge command. an example is shown in figure 25. data n + 1 is either the last of a burst of two or the last desired of a longer burst. following the pre- charge command, a subsequent command to the same bank cannot be issued until t rp is met. in the case of a fixed-length burst being executed to completion, a precharge command issued at the optimum time (as described above) provides the same operation that would result from the same fixed-length burst with auto precharge. the disadvantage of the precharge command is that it requires that the command and address buses be available at the appropriate time to issue the command; the advantage of the precharge command is that it can be used to truncate fixed-length or full-page bursts. figure 23: random write cycles figure 24: write to read don?t care clk dq d in n t2 t1 t3 t0 command address write bank, col n d in a d in x d in m write write write bank, col a bank, col x bank, col m notes: 1) each write command may be to any bank. 2) dqm is low. 3) example shows a burst of one, or an interrupting bl > 1. transitioning data don?t care clk dq t2 t1 t3 t0 command address nop write bank, col n d in n d in n + 1 d out b read nop nop bank, col b nop d out b + 1 t4 t5 notes: 1) the write command may be to any bank, and the read command may be to any bank. 2) dqm is low. 3) cas latency = 2 for illustration. 4) data n+1 is either the last data of a burst of two, or the last desired of a longer burst. transitioning data
128mb: x16, x32 mobile sdram 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobile_2.fm - rev. g (draft) 7/04 en 29 ?2001 micron technology, inc. all rights reserved. figure 25: write to precharge dqm clk dq t2 t1 t4 t3 t0 command address bank a , col n t5 nop write precharge nop nop d in n d in n + 1 active t rp bank ( a or all) t wr bank a , row dqm dq command address bank a , col n nop write precharge nop nop d in n d in n + 1 active t rp don?t care bank ( a or all) t wr note: dqm could remain low in this example if the write burst is a fixed length of two. bank a , row t6 nop nop t wr@ t ck 15ns t wr@ t ck < 15ns transitioning data
128mb: x16, x32 mobile sdram 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobile_2.fm - rev. g (draft) 7/04 en 30 ?2001 micron technology, inc. all rights reserved. fixed-length or full-page write bursts can be trun- cated with the burst terminate command. when truncating a write burst, the input data applied coin- cident with the burst terminate command will be ignored. the last data written (provided that dqm is low at that time) will be the input data applied one clock previous to the burst terminate command. this is shown in figure 26, where data n is the last desired data element of a longer burst. figure 26: terminating a write burst figure 27: precharge command precharge the precharge command (see figure 27) is used to deactivate the open row in a particular bank or the open row in all banks. the bank(s) will be available for a subsequent row access some specified time ( t rp) after the precharge command is issued. input a10 determines whether one or all banks are to be pre- charged, and in the case where only one bank is to be precharged, inputs ba0, ba1 select the bank. when all banks are to be precharged, inputs ba0, ba1 are treated as ?don?t care.? once a bank has been pre- charged, it is in the idle state and must be activated prior to any read or write commands being issued to that bank. power-down power-down occurs if cke is registered low coinci- dent with a nop or command inhibit when no accesses are in progress. if power-down occurs when all banks are idle, this mode is referred to as precharge power-down; if power-down occurs when there is a row active in any bank, this mode is referred to as active power-down. entering power-down deactivates the input and output buffers, excluding cke, for maxi- mum power savings while in standby. the device may not remain in the power-down state longer than the refresh period (64ms) since no refresh operations are performed in this mode. the power-down state is exited by registering a nop or command inhibit and cke high at the desired clock edge (meeting t cks). see figure 28. clk dq t2 t1 t0 command address bank, col n write burst terminate next command d in n (address) (data) note: dqms are low. transitioning data don?t care cs# we# cas# ras# cke clk a10 don?t care high all banks bank selected a0-a9 ba0,1 bank address valid address
128mb: x16, x32 mobile sdram 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobile_2.fm - rev. g (draft) 7/04 en 31 ?2001 micron technology, inc. all rights reserved. figure 28: power-down don?t care t ras t rcd t rc all banks idle input buffers gated off exit power-down mode. ( ) ( ) ( ) ( ) ( ) ( ) t cks > t cks command nop active enter power-down mode. nop clk cke ( ) ( ) ( ) ( )
128mb: x16, x32 mobile sdram 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobile_2.fm - rev. g (draft) 7/04 en 32 ?2001 micron technology, inc. all rights reserved. clock suspend the clock suspend mode occurs when a column access/burst is in progress and cke is registered low. in the clock suspend mode, the internal clock is deacti- vated, ?freezing? the synchronous logic. for each positive clock edge on which cke is sam- pled low, the next internal positive clock edge is sus- pended. any command or data present on the input pins at the time of a suspended internal clock edge is ignored; any data present on the dq pins remains driven; and burst counters are not incremented, as long as the clock is suspended. (see examples in figure 29 and figure 30.) figure 29: clock suspend during write burst clock suspend mode is exited by registering cke high; the internal clock and related operation will resume on the subsequent positive clock edge. burst read/single write the burst read/single write mode is entered by pro- gramming the write burst mode bit (m9) in the mode register to a logic 1. in this mode, all write com- mands result in the access of a single column location (burst of one), regardless of the programmed burst length. read commands access columns according to the programmed burst length and sequence, just as in the normal mode of operation (m9 = 0). figure 30: clock suspend during read burst don?t care d in c ommand address write bank, col n d in n nop nop clk t2 t1 t4 t3 t5 t0 cke internal clock nop d in n + 1 d in n + 2 note: for this example, burst length = 4 or greater, and dm is low. transitioning data don?t c a clk dq d out n t2 t1 t4 t3 t6 t5 t0 mand d dress read nop nop nop bank, col n nop d out n + 1 d out n + 2 d out n + 3 note: for this example, cas latency = 2, burst length = 4 or greater, a dqm is low. cke t ernal clock nop transitioning data
128mb: x16, x32 mobile sdram 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobile_2.fm - rev. g (draft) 7/04 en 33 ?2001 micron technology, inc. all rights reserved. concurrent auto precharge an access command (read or write) to another bank while an access command with auto precharge enabled is executing is not allowed by sdrams, unless the sdram supports concurrent auto precharge. micron sdrams support concurrent auto precharge. four cases where concurrent auto precharge occurs are defined below. read with auto precharge 1. interrupted by a read (with or without auto pre- charge): a read to bank m will interrupt a read on bank n , cas latency later. the precharge to bank n will begin when the read to bank m is registered (figure 31). 2. interrupted by a write (with or without auto pre- charge): a write to bank m will interrupt a read on bank n when registered. dqm should be used two clocks prior to the write command to prevent bus contention. the precharge to bank n will begin when the write to bank m is registered (figure 32). figure 31: read with auto precharge interrupted by a read don?t care clk dq d out a t2 t1 t4 t3 t6 t5 t0 command read - ap bank n nop nop nop nop d out a + 1 d out d d out d + 1 nop t7 bank n cas latency = 3 (bank m ) bank m address idle nop notes: 1) dqm is low. 2) burst length = 4 or greater 3) cas latency = 3. bank n , col a bank m , col d read - ap bank m internal states t page active read with burst of 4 interrupt burst, precharge page active read with burst of 4 precharge rp - bank n t rp - bank m cas latency = 3 (bank n ) transitioning data
128mb: x16, x32 mobile sdram 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobile_2.fm - rev. g (draft) 7/04 en 34 ?2001 micron technology, inc. all rights reserved. figure 32: read with auto precharge interrupted by a write clk dq d out a t2 t1 t4 t3 t6 t5 t0 command nop nop nop nop d in d d in d + 2 d in d + 3 nop t7 bank n bank m address idle nop dqm note: 1. dqm is high at t2 to prevent d out - a +1 from contending with d in - d at t4. bank n , col a bank m , col d write - ap bank m internal states t page active read with burst of 4 interrupt burst, precharge page active write with burst of 4 write-back rp - bank n t wr - bank m cas latency = 3 (bank n ) read - ap bank n 1 don?t care transitioning data d in d + 1
128mb: x16, x32 mobile sdram 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobile_2.fm - rev. g (draft) 7/04 en 35 ?2001 micron technology, inc. all rights reserved. write with auto precharge 3. interrupted by a read (with or without auto pre- charge): a read to bank m will interrupt a write on bank n when registered, with the data-out appearing cas latency later. the precharge to bank n will begin after t wr is met, where t wr begins when the read to bank m is registered. the last valid write to bank n will be data-in registered one clock prior to the read to bank m (figure 33). 4. interrupted by a write (with or without auto pre- charge): a write to bank m will interrupt a write on bank n when registered. the precharge to bank n will begin after t wr is met, where t wr begins when the write to bank m is registered. the last valid data write to bank n will be data registered one clock prior to a write to bank m (figure 34). figure 33: write with auto precharge interrupted by a read don?t care clk dq t2 t1 t4 t3 t6 t5 t0 command write - ap bank n nop nop nop nop d in a + 1 d in a nop nop t7 bank n bank m address note: 1. dqm is low. bank n , col a bank m , col d read - ap bank m internal states t page active write with burst of 4 interrupt burst, write-back precharge page active read with burst of 4 t t rp - bank m d out d d out d + 1 cas latency = 3 (bank m ) rp - bank n wr - bank n transitioning data
128mb: x16, x32 mobile sdram 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobile_2.fm - rev. g (draft) 7/04 en 36 ?2001 micron technology, inc. all rights reserved. figure 34: write with auto precharge interrupted by a write don?t care clk dq t2 t1 t4 t3 t6 t5 t0 command write - ap bank n nop nop nop nop d in d + 1 d in d d in a + 1 d in a + 2 d in a d in d + 2 d in d + 3 nop t7 bank n bank m address nop note: 1. dqm is low. bank n , col a bank m , col d write - ap bank m internal states t page active write with burst of 4 interrupt burst, write-back precharge page active write with burst of 4 write-back wr - bank n t rp - bank n t wr - bank m transitioning data
128mb: x16, x32 mobile sdram 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobile_2.fm - rev. g (draft) 7/04 en 37 ?2001 micron technology, inc. all rights reserved. note: 1. cke n is the logic state of cke at clock edge n; cke n-1 was the state of cke at the previous clock edge. 2. current state is the state of the sdram immediately prior to clock edge n . 3. command n is the command registered at clock edge n , and action n is a result of command n . 4. all states and sequences not shown are illegal or reserved. 5. exiting power-down at clock edge n will put the device in the all banks idle state in time for clock edge n + 1 (provided that t cks is met). 6. exiting self refresh at clock edge n will put the device in the all banks idle state once t xsr is met. command inhibit or nop commands should be issued on any clock edges occurring during the t xsr period. a minimum of two nop com- mands must be provided during t xsr period. 7. after exiting clock suspend at clock edge n , the device will resume operation and recognize the next command at clock edge n + 1. table 9: truth table ? cke (notes: 1-4) cke n-1 cke n current state command n action n notes l l power-down x maintain power-down self refresh x maintain self refresh clock suspend x maintain clock suspend l h power-down command inhibit or nop exit power-down 5 self refresh command inhibit or nop exit self refresh 6 clock suspend x exit clock suspend 7 h l all banks idle command inhibit or nop power-down entry all banks idle auto refresh self refresh entry reading or writing valid clock suspend entry h h see table 10 on page 38
128mb: x16, x32 mobile sdram 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobile_2.fm - rev. g (draft) 7/04 en 38 ?2001 micron technology, inc. all rights reserved. note: 1. this table applies when cke n-1 was high and cke n is high (see table 9 on page 37) and after t xsr has been met (if the previous state was self refresh). 2. this table is bank-specific, except where noted; i.e., the current state is for a specific bank and the commands shown are those allowed to be issued to that bank when in that state. exceptions are covered in the notes below. 3. current state definitions: idle: the bank has been precharged, and t rp has been met. row active: arow in the bank has been activated, and t rcd has been met. no data bursts/accesses and no register accesses are in progress. read: a read burst has been initiated, with auto precharge disabled, and has not yet termi- nated or been terminated. write: a write burst has been initiated, with auto precharge disabled, and has not yet termi- nated or been terminated. 4. the following states must not be interrupted by a command issued to the same bank. command inhibit or nop com- mands, or allowable commands to the other bank should be issued on any clock edge occurring during these states. allowable commands to the other bank are determined by its current state and table 10 on page 38, and according to table 11 on page 40. precharging: starts with registration of a precharge command and ends when t rp is met. once t rp is met, the bank will be in the idle state. row activating: starts with registration of an active command and ends when t rcd is met. once t rcd is met, the bank will be in the row active state. read w/auto precharge enabled: starts with registration of a read command with auto precharge enabled and ends when t rp has been met. once t rp is met, the bank will be in the idle state. write w/auto precharge enabled: starts with registration of a write command with auto precharge enabled and ends when t rp has been met. once t rp is met, the bank will be in the idle state. 5. the following states must not be interrupted by any ex ecutable command; command inhibit or nop commands must be applied on each positive clock edge during these states. refreshing: starts with registration of an auto refresh command and ends when t rfc is met. once t rfc is met, the sdram will be in the all banks idle state. accessing mode register: starts with registration of a load mode register command and ends when t mrd has been met. once t mrd is met, the sdram will be in the all banks idle state. precharging all: starts with registration of a precharge all command and ends when t rp is met. once t rp is met, all banks will be in the idle state. 6. all states and sequences not shown are illegal or reserved. table 10: truth table ? current state bank n , command to bank n notes: 1-6; notes appear below table current state cs# ras# cas# we# command (action) notes any hxxx command inhibit (nop/continue previous operation) l hhh no operation (nop/continue previous operation) idle l l h h active (select and activate row) lllh auto refresh 7 llll load mode register 7 llhl precharge 11 row activelhlh read (select column and start read burst) 10 lhl l write (select column and start write burst) 10 llhl precharge (deactivate row in bank or banks) 8 read (auto precharge disabled) lhlh read (select column and start new read burst) 10 lhl l write (select column and start write burst) 10 llhl precharge (truncate read burst, start precharge) 8 lhhl burst terminate 9 write (auto precharge disabled) lhlh read (select column and start read burst) 10 lhl l write (select column and start new write burst) 10 llhl precharge (truncate write burst, start precharge) 8 lhhl burst terminate 9
128mb: x16, x32 mobile sdram 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobile_2.fm - rev. g (draft) 7/04 en 39 ?2001 micron technology, inc. all rights reserved. 7. not bank-specific; requires that all banks are idle. 8. may or may not be bank-specific; if all banks are to be precharged, all must be in a valid state for precharging. 9. not bank-specific; burst terminate affects the mo st recent read or write burst, regardless of bank. 10. reads or writes listed in the command (action) column include reads or writes with auto precharge enabled and reads or writes with auto precharge disabled. 11. does not affect the state of the bank and acts as a nop to that bank.
128mb: x16, x32 mobile sdram 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobile_2.fm - rev. g (draft) 7/04 en 40 ?2001 micron technology, inc. all rights reserved. note: 1. this table applies when cke n-1 was high and cke n is high (see table 9 on page 37) and after t xsr has been met (if the previous state was self refresh). 2. this table describes alternate bank operation, except where noted; i.e., the current state is for bank n and the com- mands shown are those allowed to be issued to bank m (assu ming that bank m is in such a state that the given com- mand is allowable). exceptions are covered in the notes below. 3. current state definitions: idle: the bank has been precharged, and t rp has been met. row active: a row in the bank has been activated, and t rcd has been met. no data bursts/accesses and no register accesses are in progress. read: a read burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. write: a write burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. read w/auto precharge enabled: starts with registration of a read command with auto precharge enabled, and ends when t rp has been met. once t rp is met, the bank will be in the idle state. write w/auto precharge enabled: starts with registration of a write command with auto precharge enabled, and ends when t rp has been met. once t rp is met, the bank will be in the idle state. 4. auto refresh, self refresh and load mode register commands may only be issued when all banks are idle. 5. a burst terminate command cannot be issued to another bank; it applies to the bank represented by the current state only. 6. all states and sequences not shown are illegal or reserved. table 11: truth table ? current state bank n, command to bank m notes: 1-6; notes appear below and on next page current state cs# ras# cas# we# command (action) notes any h x x x command inhibit (nop/continue previous operation) lhhh no operation (nop/continue previous operation) idle x x x x any command otherwise allowed to bank m row activating, active, or precharging llhh active (select and activate row) lhl h read (select column and start read burst) 7 lhl l write (select column and start write burst) 7 llhl precharge read (auto precharge disabled) llhh active (select and activate row) lhl h read (select column and start new read burst) 7, 10 lhl l write (select column and start write burst) 7, 11 llhl precharge 9 write (auto precharge disabled) llhh active (select and activate row) lhl h read (select column and start read burst) 7, 12 lhl l write (select column and start new write burst) 7, 13 llhl precharge 9 read (with auto precharge) llhh active (select and activate row) lhl h read (select column and start new read burst) 7, 8, 14 lhl l write (select column and start write burst) 7, 8, 15 llhl precharge 9 write (with auto precharge) llhh active (select and activate row) lhl h read (select column and start read burst) 7, 8, 16 lhl l write (select column and start new write burst) 7, 8, 17 llhl precharge 9
128mb: x16, x32 mobile sdram 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobile_2.fm - rev. g (draft) 7/04 en 41 ?2001 micron technology, inc. all rights reserved. 7. reads or writes to bank m listed in the command (acti on) column include reads or writes with auto precharge enabled and reads or writes with auto precharge disabled. 8. concurrent auto precharge: bank n will initiate the au to precharge command when its burst has been interrupted by bank m?s burst. 9. burst in bank n continues as initiated. 10. for a read without auto precharge interrupted by a read (w ith or without auto precharge), the read to bank m will interrupt the read on bank n, cas latency later (figure 14). 11. for a read without auto precharge interrupted by a write (with or without auto precharge), the write to bank m will interrupt the read on bank n when registered (figure 16 and figure 17). dqm should be used one clock prior to the write command to prevent bus contention. 12. for a write without auto precharge interrupted by a read (with or without auto precharge), the read to bank m will interrupt the write on bank n when registered (figure 24), wi th the data-out appearing cas latency later. the last valid write to bank n will be data-in registered one clock prior to the read to bank m. 13. for a write without auto precharge interrupted by a writ e (with or without auto precharge), the write to bank will interrupt the write on bank n when registered (figure 22). the last valid write to bank n will be data-in registered one clock prior to the read to bank m. 14. for a read with auto precharge interrupted by a read (w ith or without auto precharge), the read to bank m will interrupt the read on bank n, cas latency later. the precharge to bank n will begin when the read to bank m is reg- istered (figure 31). 15. for a read with auto precharge interrupted by a write (w ith or without auto precharge), the write to bank m will interrupt the read on bank n when registered. dqm should be used two clocks prior to the write command to prevent bus contention. the precharge to bank n will begin when the write to bank m is registered (figure 32). 16. for a write with auto precharge interrupted by a read (w ith or without auto precharge), the read to bank m will interrupt the write on bank n when registered, with the data-out appearing cas latency later. the precharge to bank n will begin after t wr is met, where t wr begins when the read to bank m is registered. the last valid write bank n will be data-in registered one clock prior to the read to bank m (figure 33). 17. for a write with auto precharge interrupted by a write (w ith or without auto precharge), the write to bank m will interrupt the write on bank n when registered. the precharge to bank n will begin after t wr is met, where t wr begins when the write to bank m is registered. the last valid write to bank n will be data registered one clock to the write to bank m (figure 34).
128mb: x16, x32 mobile sdram 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobile_2.fm - rev. g (draft) 7/04 en 42 ?2001 micron technology, inc. all rights reserved. absolute maximum ratings voltage on v dd /v dd q supply relative to v ss (lc devices) . . . . . . . . . . .-1v to +4.6v relative to v ss (v devices) . . . . . . . . . . . 0.5v to +3.6v voltage on inputs, nc or i/o pins relative to v ss (lc, devices) . . . . . . . . . .-1v to +4.6v relative to v ss (v devices) . . . . . . . . . . -0.5v to +3.6v operating temperature t a (commercial) . . . . . . . . . . . . . . . . . . . 0c to +70c t a (industrial) . . . . . . . . . . . . . . . . . . . -40c to +85c t a (extended) . . . . . . . . . . . . . . . . . . . -25c to +75c storage temperature (plastic) . . . . -55c to +150c stresses greater than those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other condi- tions above those indicated in the operational sections of this specification is not implied. exposure to abso- lute maximum rating conditions for extended periods may affect reliability. table 12: dc electrical characteristics and operating conditions (lc version) notes: 1, 6; notes appear on page 47; v dd = +3.3v 0.3v, v dd q = +3.3v 0.3v parameter/condition symbol min max units notes supply voltage v dd 33.6v i/o supply voltage v dd q33.6v input high voltage: logic 1; all inputs v ih 2v dd + 0.3 v 22 input low voltage: logic 0; all inputs v il -0.3 0.8 v 22 data output high voltage: logic 1; all inputs v oh 2.4 ? v data output low voltage: logic 0; all inputs v ol ?0.4v input leakage current: any input 0v vin v dd (all other pins not under test = 0v) i i -5 5 a output leakage current: dqs are disabled; 0v vout v dd q i oz -5 5 a table 13: dc electrical characteristics and operating conditions (v version) notes: 1, 6; notes appear on page 47; v dd = 2.5 0.2v, v dd q = +2.5v 0.2v or +1.8v 0.15v parameter/condition symbol min max units notes supply voltage v dd 2.3 2.7 v i/o supply voltage v dd q 1.65 2.7 v input high voltage: logic 1; all inputs v ih (dq) 1.25 v dd q + 0.3 v 22 v ih (non-dq) 1.25 v dd + 0.3 input low voltage: logic 0; all inputs v il -0.3 +0.55 v 22 data output high voltage: logic 1; all inputs v oh v dd q - 0.2 ? v data output low voltage: logic 0; all inputs v ol ?0.2v input leakage current: any input 0v vin v dd (all other pins not under test = 0v) i i -5 5 a output leakage current: dqs are disabled; 0v vout v dd q i oz -5 5 a
128mb: x16, x32 mobile sdram 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobile_2.fm - rev. g (draft) 7/04 en 43 ?2001 micron technology, inc. all rights reserved. table 14: electrical characteristics and recommended ac operating conditions notes: 5, 6, 7, 8, 9, 11; notes appear on page 47 ac characteristics parameter symbol -75m -8 -10 units notes min max min max min max access time from clk (positive. edge) cl = 3 t ac (3) 5.4 7 7 ns cl = 2 t ac (2) 6 8 8 ns cl = 1 t ac (1) na 19 22 ns address hold time t ah0.811ns address setup time t as 1.5 2.5 2.5 ns clk high-level width t ch3 33ns clk low-level width t cl2.533ns clock cycle time cl = 3 t ck (3) 7.5 8 10 ns 23 cl = 2 t ck (2) 9.6 9.6 12 ns 23 cl = 1 t ck (1) n/a 20 25 ns 23 cke hold time t ckh1 11ns cke setup time t cks 2.5 2.5 2.5 ns cs#, ras#, cas#, we#, dqm hold time t cmh0.811ns cs#, ras#, cas#, we#, dqm setup time t cms 1.5 2.5 2.5 ns data-in hold time t dh0.811ns data-in setup time t ds 1.5 2.5 2.5 ns data-out high-impedance time cl = 3 t hz (3) 5.4 7 7 ns 10 cl = 2 t hz (2) 6 8 8 ns 10 cl = 1 t hz (1) na 19 22 ns 10 data-out low-impedance time t lz1 11ns data-out hold time (load) t oh 2.5 2.5 2.5 ns 27 data-out hold time (no load) t oh n 1.8 1.8 1.8 ns active to precharge command t ras 44 120,000 48 120,000 50 120,000 ns active to active command period t rc 66 80 100 ns active to read or write delay t rcd 19 20 20 ns refresh period (4,096 rows) t ref 64 64 64 ms auto refresh command period t rfc 66 80 100 ns precharge command period t rp 19 20 20 ns active bank a to active bank b command t rrd 2 2 2 t ck transition time t t 0.3 1.2 0.5 1.2 0.5 1.2 ns 7 write recovery time auto precharge mode manual precharge mode t wr (a) 1 clk +7.5ns 1 clk +7ns 1 clk +5ns ?24 t wr (m) 15 15 15 ns 25 exit self refresh to active command t xsr 67 80 100 ns 20
128mb: x16, x32 mobile sdram 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobile_2.fm - rev. g (draft) 7/04 en 44 ?2001 micron technology, inc. all rights reserved. table 15: ac functional characteristics notes: 5, 6, 7, 8, 9, 11; notes appear on page 47 parameter symbol -75m -8 -10 units notes read/write command to read/write command t ccd 1 1 1 t ck 17 cke to clock disable or power-down entry mode t cked 1 1 1 t ck 14 cke to clock enable or power-down exit setup mode t ped 1 1 1 t ck 14 dqm to input data delay t dqd 0 0 0 t ck 17 dqm to data mask during writes t dqm 0 0 0 t ck 17 dqm to data high-impedance during reads t dqz 2 2 2 t ck 17 write command to input data delay t dwd 0 0 0 t ck 17 data-in to active command t dal 5 5 5 t ck 15, 21 data-in to precharge command t dpl 2 2 2 t ck 16, 21 last data-in to burst stop command t bdl 1 1 1 t ck 17 last data-in to new read/write command t cdl 1 1 1 t ck 17 last data-in to precharge command t rdl 2 2 2 t ck 16, 21 load mode register command to active or refresh command t mrd 2 2 2 t ck 26 data-out to high-impedance from precharge command cl = 3 t roh(3) 3 3 3 t ck 17 cl = 2 t roh(2) 2 2 2 t ck 17 cl = 1 t roh(1) 1 1 t ck 17
128mb: x16, x32 mobile sdram 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobile_2.fm - rev. g (draft) 7/04 en 45 ?2001 micron technology, inc. all rights reserved. ta bl e 1 6 : i dd specifications and conditions (x16) notes: 1, 3, 6, 11, 13, 31 ; notes appear on page 47; v dd = v dd q = +3.3v 0.3v or v dd = v dd q = 2.5v 0.2v or v dd = +2.5v 0.2v, v dd q = +1.8v 0.15v max parameter/condition symbol -75m -8 -10 units notes operating current: active mode; burst = 2; read or write; t rc = t rc (min) i dd1 130 100 100 ma 18, 19 standby current: power-down mode; all banks idle; cke = low i dd2 450 450 450 a 12, 33 standby current: active mode; cke = high; cs# = high; all banks active after t rcd met; no accesses in progress i dd3 40 35 35 ma 19 operating current: burst mode; page burst; read or write; all banks active i dd4 115 100 95 ma 18, 19 auto refresh current cke = high; cs# = high t rfc = t rfc (min) i dd5 225 210 170 ma 12, 18, 19, 32, 33 t rfc = 15.625s i dd6 333ma ta bl e 1 7 : i dd 7 self refresh current options (x16) notes: 4 appears on page 47; v dd = v dd q = +3.3v 0.3v or v dd = v dd q = 2.5v 0.2v or v dd = +2.5v 0.2v, v dd q = +1.8v 0.15v temperature compensated self refresh (tcsr) parameter/condition max temperature -75m, -8, -10 units self refresh current: cke < 0.2v (e4 = 1, e3=1) 85oc 800 a self refresh current: cke < 0.2v (e4 = 0, e3=0) 70oc 500 a self refresh current: cke < 0.2v (e4 = 0, e3=1) 45oc 350 a self refresh current: cke < 0.2v (e4 = 1, e3=0) 15oc 300 a
128mb: x16, x32 mobile sdram 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobile_2.fm - rev. g (draft) 7/04 en 46 ?2001 micron technology, inc. all rights reserved. ta bl e 1 8 : i dd specifications and conditions (x32) notes: 1, 3, 6, 11, 13, 31 ; notes appear on page 47; v dd = v dd q = +3.3v 0.3v or v dd = v dd q = 2.5v 0.2v or v dd = +2.5v 0.2v, v dd q = +1.8v 0.15v max parameter/condition symbol -75m -8 -10 units notes operating current: active mode; burst = 2; read or write; t rc = t rc (min) i dd1 150 120 120 ma 18, 19 standby current: power-down mode; all banks idle; cke = low i dd2 450 450 450 a 12, 33 standby current: active mode; cke = high; cs# = high; all banks active after t rcd met; no accesses in progress i dd3 45 40 40 ma 19 operating current: burst mode; page burst; read or write; all banks active i dd4 130 115 110 ma 18, 19 auto refresh current cke = high; cs# = high t rfc = t rfc (min) i dd5 235 220 180 ma 12, 18, 19, 32, 33 t rfc = 15.625s i dd6 333ma ta bl e 1 9 : i dd 7 self refresh current options (x32) notes: 4 appears on page 47; v dd = v dd q = +3.3v 0.3v or v dd = v dd q = 2.5v 0.2v or v dd = +2.5v 0.2v, v dd q = +1.8v 0.15v temperature compensated self refresh (tcsr) parameter/condition max temperature -75m, -8, -10 units self refresh current: cke < 0.2v (e4 = 1, e3=1) 85oc 1000 a self refresh current: cke < 0.2v (e4 = 0, e3=0) 70oc 550 a self refresh current: cke < 0.2v (e4 = 0, e3=1) 45oc 400 a self refresh current: cke < 0.2v (e4 = 1, e3=0) 15oc 350 a table 20: capacitance (fbga pacakge) (note; 2 notes appear on page 47) parameter symbol min max units notes input capacitance: clk c i1 1.5 3.5 pf 28 input capacitance: all other input-only pins c i2 1.5 3.8 pf 29 input/output capacitance: dqs c io 3.0 6.0 pf 30 table 21: capacitance (tsop pacakge) (note; 2 notes appear on page 47) parameter symbol min max units notes input capacitance: clk c i1 2.5 3.5 pf 28 input capacitance: all other input-only pins c i2 2.5 3.8 pf 29 input/output capacitance: dqs c io 4.0 6.0 pf 30
128mb: x16, x32 mobile sdram 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobile_2.fm - rev. g (draft) 7/04 en 47 ?2001 micron technology, inc. all rights reserved. notes 1. all voltages are referenced to vss 2. this parameter is sampled. v dd , v dd q = +3.3v; t a = 25c; pin under test biased at 1.4v., f = 1 mhz, 3. i dd is dependent on output loading and cycle rates. specified values are obtained with mini- mum cycle time and the outputs open. 4. enables on-chip refresh and address counters. 5. the minimum specifications are used only to indicate cycle time at which proper operation over the full operational temperature range is ensured ( t a = commercial, it or xt). 6. an initial pause of 100s is required after power- up, followed by two auto refresh commands, before proper device operation is ensured. (v dd and v dd q must be powered up simultaneously. v ss and v ss q must be at same potential.) the two auto refresh command wake-ups should be repeated any time the t ref refresh requirement is exceeded. 7. ac characteristics assume t t = 1ns. 8. in addition to meeting the transition rate specifi- cation, the clock and cke must transit between v ih and v il (or between v il and v ih ) in a mono- tonic manner. 9. outputs measured at 1.5v (for lc devices) or at 1.25v (v devices) with equivalent load: 10. t hz defines the time at which the output achieves the open circuit condition; it is not a reference to v oh or v ol . the last valid data element will meet t oh before going high-z. 11. ac timing and i dd tests use established values for v il and v ih , with timing referenced to v ih /2 crossover point. if the input transition time is longer than 1ns, then the timing is referenced at v il ( max ) and v ih ( min ) and no longer at the v ih /2 crossover point. established tester values follow: v il = 0v, v ih = 3.0v for lc devices, and v ih = 2.3v for v devices. 12. other input signals are allowed to transition no more than once every two clocks and are other- wise at valid v ih or v il levels. 13. i dd specifications are tested after the device is properly initialized. 14. timing actually specified by t cks; clock(s) speci- fied as a reference only at minimum cycle rate. 15. timing actually specified by t wr plus t rp; clock(s) specified as a reference only at minimum cycle rate. 16. timing actually specified by t wr. 17. required clocks are specified by jedec function- ality and are not dependent on any timing param- eter. 18. the i dd current will increase or decrease propor- tionally according to the amount of frequency alteration for the test condition. 19. address transitions average one transition every two clocks. 20. clk must be toggled a minimum of two times during this period. 21. based on t ck = 125mhz for -8 and t ck = 100mhz for -10. 22. v ih overshoot: v ih (max) = v dd q + 2v for a pulse width 3ns, and the pulse width cannot be greater than one third of the cycle rate. v il under- shoot: v il (min) = -2v for a pulse width 3ns and can not be greater than one third of the cycle rate. 23. the clock frequency must remain constant (stable clock is defined as a signal cycling within timing constraints specified for the clock pin) during access or precharge states (read, write, includ- ing t wr, and precharge commands). cke may be used to reduce the data rate. 24. auto precharge mode only. the precharge timing budget ( t rp) begins at 5.4ns for -8 after the first clock delay, after the last write is executed. 25. manual precharge mode only. 26. jedec and pc100 specify three clocks. 27. parameter guaranteed by design. 28. pc100 specifies a maximum of 4pf. 29. pc100 specifies a maximum of 5pf. 30. pc100 specifies a maximum of 6.5pf. 31. for -75m, cl=3 and t ck = 7.5ns; for -8, cl = 3 and t ck = 8ns; for -10, cl = 3 and t ck =10ns. 32. cke is high during refresh command period t rfc (min) else cke is low. the i dd 6 limit is actually a nominal value and does not result in a fail value. 33. specified with i/os in steady state condition. q 30pf
128mb: x16, x32 mobile sdram 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobile_2.fm - rev. g (draft) 7/04 en 48 ?2001 micron technology, inc. all rights reserved. figure 35: initialize and load mode register note: 1. the two auto refresh commands at t9 and t19 may be applied before either load mode register (lmr) command. 2. pre = precharge command, lmr = load mode register command, ar = auto refresh command, act = active command, ra = row address, ba = bank address 3. the load mode register for both mr/emr and 2 auto refresh commands can be in any order. however, all must occur prior to an active command 4. optional refresh command. 5. although not required, to prevent bus contention it is suggested to keep dqm high during the initialization sequence. see table 14, electrical characteristics and recommended ac operating conditions, on page 43 cke ba0, ba1 load extended mode register load mode register t cks power-up: v dd and clk stable t = 100s t ckh ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) dqml, dqmu 5 ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) dq high-z a0-a9, a11 ra a10 ra all banks clk t ck lmr 3 nop pre lmr 3 ar ar 4 act t cms t cmh ba0 = l, ba1 = h t as t ah t as t ah ba0 = l, ba1 = l ( ) ( ) ( ) ( ) code code t as t ah code code ( ) ( ) ( ) ( ) pre all banks t as t ah ( ) ( ) ( ) ( ) t0 t1 t3 t5 t7 t9 t19 t29 don?t care ba ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) t rp t mrd t mrd t rp t rfc t rfc ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) command 1,2
128mb: x16, x32 mobile sdram 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobile_2.fm - rev. g (draft) 7/04 en 49 ?2001 micron technology, inc. all rights reserved. figure 36: power-down mode note: 1. violating refresh requirements during power-down may result in a loss of data. see table 14, electrical characteristics and recommended ac operating conditions, on page 43 t ch t cl t ck two clock cycles cke 1 clk dq all banks idle, enter power-down mode precharge all active banks input buffers gated off while in power-down mode exit power-down mode ( ) ( ) ( ) ( ) don?t care t cks t cks command t cmh t cms precharge nop nop active nop ( ) ( ) ( ) ( ) all banks idle ba0, ba1 bank bank(s) ( ) ( ) ( ) ( ) high-z t ah t as t ckh t cks dqml, dqmu ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) a0-a9, a11 row ( ) ( ) ( ) ( ) all banks single bank a10 row ( ) ( ) ( ) ( ) t0 t1 t2 tn + 1 tn + 2
128mb: x16, x32 mobile sdram 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobile_2.fm - rev. g (draft) 7/04 en 50 ?2001 micron technology, inc. all rights reserved. figure 37: clock suspend mode note: 1. for this example, the burst length = 2, the cas latency = 3, and auto precharge is disabled. 2. x16:a9 and a11 = ?don?t care? x32:a8, a9 and a11 = ?don?t care? see table 14, electrical characteristics and recommended ac operating conditions, on page 43 t ch t cl t ac t lz dqmu, dqml clk a0-a9, a11 2 dq ba0, ba1 a10 t oh d out m t ah t as t ah t as t ah t as bank t dh d in e t ac t hz d out m + 1 command 1 t cmh t cms nop nop nop nop nop read write cke t cks t ckh bank column m t ds d in e + 1 nop t ckh t cks t cmh t cms 2 column e 2 t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t ck don?t care undefined
128mb: x16, x32 mobile sdram 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobile_2.fm - rev. g (draft) 7/04 en 51 ?2001 micron technology, inc. all rights reserved. figure 38: auto refresh mode note: 1. each auto refresh command performs a refresh cycle. back-to-back commands are not required. see table 14, electrical characteristics and recommended ac operating conditions, on page 43 t ch t cl t ck cke clk dq t rfc 1 ( ) ( ) ( ) ( ) ( ) ( ) t rp ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) command t cmh t cms nop nop ( ) ( ) ( ) ( ) bank active auto refresh ( ) ( ) ( ) ( ) nop nop precharge precharge all active banks auto refresh t rfc 1 high-z ba0, ba1 bank(s) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) t ah t as t ckh t cks ( ) ( ) nop ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) dqmu, dqml a0-a9, a11 row ( ) ( ) ( ) ( ) all banks single bank a10 row ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) t0 t1 t2 tn + 1 to + 1 don?t care
128mb: x16, x32 mobile sdram 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobile_2.fm - rev. g (draft) 7/04 en 52 ?2001 micron technology, inc. all rights reserved. figure 39: self refresh mode note: 1. no maximum time limit for self refresh. t ras (max) only applies to non-self refresh mode. 2. t xsr requires a minimum of two clocks regardless of frequency or timing. 3. as a general rule, any time self refresh is exited, the dram may not re-enter the self refresh mode until all rows have been refreshed via the auto refresh command at the distributed refresh rate, ( t ref / number of rows), or faster. how- ever, the following exception is allowed. self refresh mode may be re-entered any time after exiting, if the following conditions are all met: a.) the dram has been in the self refresh mode for a minimum of 64ms prior to exiting. b.) t xsr has not been violated. c.) at least two auto refresh commands are performed du ring each 15.625us interval while the dram remains out of the self refresh mode. see table 14, electrical characteristics and recommended ac operating conditions, on page 43 don?t care t ch t cl t ck t rp cke clk dq enter self refresh mode precharge all active banks t xsr 2 clk stable prior to exiting self refresh mode exit self refresh mode (restart refresh time base) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) command t cmh t cms auto refresh precharge nop nop ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ba0, ba1 bank(s) high-z t cks ah as auto refresh > t ras 1 ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) t ckh t cks dqmu, dqml ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) t t a0-a9, a11 ( ) ( ) ( ) ( ) all banks single bank a10 ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) t0 t1 t2 tn + 1 to + 1 to + 2 ( ) ( ) ( ) ( )
128mb: x16, x32 mobile sdram 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobile_2.fm - rev. g (draft) 7/04 en 53 ?2001 micron technology, inc. all rights reserved. figure 40: read ? without auto precharge note: 1. for this example, the burst length = 4, the cas latency = 2, and the read burst is followed by a ?manual? precharge. 2. x16:a9 and a11 = ?don?t care? x32:a8, a9,and a11 = ?don?t care? see table 14, electrical characteristics and recommended ac operating conditions, on page 43 all banks t ch t cl t ac t lz t rp t ras t rcd cas latency t rc t oh d out m t cmh t cms t ah t as t ah t as t ah t as row row bank bank(s) bank row row bank t hz t oh d out m +3 t ac t oh t ac t oh t ac d out m +2 d out m +1 t cmh t cms precharge nop nop nop active nop read nop active disable auto precharge single banks don?t care undefined column m 2 t ckh t cks t0 t1 t2 t3 t4 t5 t6 t7 t8 dqmu, dqml cke clk a0-a9, a11 dq ba0, ba1 a10 command t ck
128mb: x16, x32 mobile sdram 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobile_2.fm - rev. g (draft) 7/04 en 54 ?2001 micron technology, inc. all rights reserved. figure 41: read ? with auto precharge note: 1. for this example, the burst length = 4, the cas latency = 2. 2. x16:a9 and a11 = ?don?t care? x32:a8, a9,and a11 = ?don?t care? see table 14, electrical characteristics and recommended ac operating conditions, on page 43 enable auto precharge t ch t cl t ac t lz t rp t ras t rcd cas latency t rc dqmu, dqml cke clk a0-a9, a11 dq ba0, ba1 a10 t oh d out m t cmh t cms t ah t as t ah t as t ah t as row row bank bank row row bank don?t care undefined t hz t oh d out m + 3 t ac t oh t ac t oh t ac d out m + 2 d out m + 1 command t cmh t cms nop nop nop active nop read nop active nop t ckh t cks column m 2 t0 t1 t2 t4 t3 t5 t6 t7 t8 t ck
128mb: x16, x32 mobile sdram 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobile_2.fm - rev. g (draft) 7/04 en 55 ?2001 micron technology, inc. all rights reserved. figure 42: single read ? without auto precharge note: 1. for this example, the burst length = 4, the cas latency = 2, and the read burst is followed by a ?manual? precharge. 2. x16:a9 and a11 = ?don?t care? x32:a8, a9,and a11 = ?don?t care? 3. precharge command not allowed or t ras would be violated. see table 14, electrical characteristics and recommended ac operating conditions, on page 43 all banks t ch t cl t ac t lz t rp t ras t rcd cas latency t rc t oh d out m t cmh t cms t ah t as t ah t as t ah t as row row bank bank(s) bank row row bank t hz t cmh t cms nop nop nop precharge active nop read active nop disable auto precharge single banks don?t care undefined column m 2 t ckh t cks t0 t1 t2 t3 t4 t5 t6 t7 t8 dqmu, dqml cke clk a0-a9, a11 dq ba0, ba1 a10 command 3 3 t ck
128mb: x16, x32 mobile sdram 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobile_2.fm - rev. g (draft) 7/04 en 56 ?2001 micron technology, inc. all rights reserved. figure 43: single read ? with auto precharge note: 1. for this example, the burst length = 4, the cas latency = 2, and the read burst is followed by a ?manual? precharge. 2. x16:a9 and a11 = ?don?t care? x32:a8, a9,and a11 = ?don?t care? 3. precharge command not allowed or t ras would be violated. see table 14, electrical characteristics and recommended ac operating conditions, on page 43 enable auto precharge t ch t cl t rp t ras t rcd cas latency t rc dqmu, dqml cke clk a0-a9, a11 dq ba0, ba1 a10 t cmh t cms t ah t as t ah t as t ah t as row row bank bank row row bank t hz t oh d out m t ac command t cmh t cms nop 3 read active nop nop 3 active nop t ckh t cks column m 2 t0 t1 t2 t4 t3 t5 t6 t7 t8 nop nop don?t care undefined t ck
128mb: x16, x32 mobile sdram 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobile_2.fm - rev. g (draft) 7/04 en 57 ?2001 micron technology, inc. all rights reserved. figure 44: alternating bank read accesses note: 1. for this example, the burst length = 4, the cas latency = 2. 2. x16:a9 and a11 = ?don?t care? x32:a8, a9,and a11 = ?don?t care.? see table 14, electrical characteristics and recommended ac operating conditions, on page 43 enable auto precharge t ch t cl t ac t lz dqmu, dqml clk a0-a9, a11 dq ba0, ba1 a10 t oh d out m t cmh t cms t ah t as t ah t as t ah t as row row row row t oh d out m + 3 t ac t oh t ac t oh t ac d out m + 2 d out m + 1 command t cmh t cms nop nop active nop read nop active t oh d out b t ac t ac read enable auto precharge row active row bank 0 bank 0 bank 3 bank 3 bank 0 cke t ckh t cks column m 2 column b 2 t0 t1 t2 t4 t3 t5 t6 t7 t8 t rp - bank 0 t ras - bank 0 t rcd - bank 0 t rcd - bank 0 cas latency - bank 0 t rcd - bank 3 cas latency - bank 3 t t rc - bank 0 rrd t ck don?t care undefined
128mb: x16, x32 mobile sdram 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobile_2.fm - rev. g (draft) 7/04 en 58 ?2001 micron technology, inc. all rights reserved. figure 45: read ? full-page burst note: 1. for this example, the cas latency = 2. 2. x16:a9 and a11 = ?don?t care? x32:a8, a9,and a11 = ?don?t care? 3. page left open; no t rp. see table 14, electrical characteristics and recommended ac operating conditions, on page 43 t ac t lz t rcd cas latency dqmu, dqml cke clk a0-a9, a11 dq ba0, ba1 a10 t oh d out m t cmh t cms t ah t as t ah t as t ac t oh d out m +1 row row t hz t ac t oh d out m +1 t ac t oh d out m +2 t ac t oh d out m -1 t ac t oh d out m full-page burst does not self-terminate. can use burst terminate command. ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) full page completed 512 (x16) locations within same row command t cmh t cms nop nop nop active nop read nop burst term nop nop ( ) ( ) ( ) ( ) nop ( ) ( ) ( ) ( ) t ah t as bank ( ) ( ) ( ) ( ) bank t ckh t cks ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) column m 2 3 t0 t1 t2 t4 t3 t5 t6 tn + 1 tn + 2 tn + 3 tn + 4 don?t care undefined t ch t ck t cl
128mb: x16, x32 mobile sdram 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobile_2.fm - rev. g (draft) 7/04 en 59 ?2001 micron technology, inc. all rights reserved. figure 46: read ? dqm operation note: 1. for this example, the cas latency = 2. 2. x16:a9 and a11 = ?don?t care? x32:a8, a9,and a11 = ?don?t care? see table 14, electrical characteristics and recommended ac operating conditions, on page 43 t ch t cl t rcd cas latency dqmu, dqml cke clk a0-a9, a11 dq ba0, ba1 a10 t cms row bank row bank t ac lz d out m t oh d out m + 3 d out m + 2 t t hz lz t t cmh command nop nop nop active nop read nop nop nop t hz t ac t oh t ac t oh t ah t as t cms t cmh t ah t as t ah t as t ckh t cks enable auto precharge disable auto precharge column m 2 t0 t1 t2 t4 t3 t5 t6 t7 t8 t ck don?t care undefined
128mb: x16, x32 mobile sdram 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobile_2.fm - rev. g (draft) 7/04 en 60 ?2001 micron technology, inc. all rights reserved. figure 47: write ? without auto precharge note: 1. for this example, the burst length = 4, and the write burst is followed by a ?manual? precharge. 2. 15ns is required between and the precharge command, regardless of frequency. 3. x16: a9 and a11 = ?don?t care? x32: a8, a9,and a11 = ?don?t care? see table 14, electrical characteristics and recommended ac operating conditions, on page 43 disable auto precharge all banks t ch t cl t rp t ras t rcd t rc dqmu, dqml cke clk a0-a9, a11 dq ba0, ba1 a10 t cmh t cms t ah t as row row bank bank bank row row bank t wr d in m t dh t ds d in m + 1 d in m + 2 d in m + 3 command t cmh t cms nop nop nop active nop write nop precharge active t ah t as t ah t as t dh t ds t dh t ds t dh t ds single bank t ckh t cks column m 3 2 t0 t1 t2 t4 t3 t5 t6 t7 t8 t9 nop don?t care undefined t ck
128mb: x16, x32 mobile sdram 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobile_2.fm - rev. g (draft) 7/04 en 61 ?2001 micron technology, inc. all rights reserved. figure 48: write ? with auto precharge note: 1. for this example, the burst length = 4. 2. x16: a9 and a11 = ?don?t care? x32: a8, a9,and a11 = ?don?t care? see table 14, electrical characteristics and recommended ac operating conditions, on page 43 enable auto precharge t ch t cl t rp t ras t rcd t rc dqmu, dqml cke clk a0-a9, a11 dq ba0, ba1 a10 t cmh t cms t ah t as row row bank bank row row bank t wr d in m t dh t ds d in m + 1 d in m + 2 d in m + 3 command t cmh t cms nop nop nop active nop write nop active t ah t as t ah t as t dh t ds t dh t ds t dh t ds t ckh t cks nop nop column m 2 t0 t1 t2 t4 t3 t5 t6 t7 t8 t9 don?t care t ck
128mb: x16, x32 mobile sdram 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobile_2.fm - rev. g (draft) 7/04 en 62 ?2001 micron technology, inc. all rights reserved. figure 49: single write ? without auto precharge note: 1. for this example, the burst length = 1, and the write burst is followed by a ?manual? precharge. 2. 15ns is required between and the precharge command, regardless of frequency. 3. x16:a9 and a11 = ?don?t care? x32:a8, a9,and a11 = ?don?t care? 4. precharge command not allowed else t ras would be violated. see table 14, electrical characteristics and recommended ac operating conditions, on page 43 disable auto precharge all banks t ch t cl t rp t ras t rcd t rc dqmu, dqml cke clk a0-a9, a11 dq ba0, ba1 a10 t cmh t cms t ah t as row bank bank bank row row bank t wr d in m t dh t ds command t cmh t cms nop 4 nop 4 precharge active nop write active nop nop t ah t as t ah t as single bank t ckh t cks column m 3 2 t0 t1 t2 t4 t3 t5 t6 t7 t8 don?t care t ck
128mb: x16, x32 mobile sdram 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobile_2.fm - rev. g (draft) 7/04 en 63 ?2001 micron technology, inc. all rights reserved. figure 50: single write ? with auto precharge note: 1. for this example, the burst length = 1, and the write burst is followed by a ?manual? precharge. 2. 15ns is required between and the precharge command, regardless of frequency. 3. x16:a9 and a11 = ?don?t care? x32:a8, a9,and a11 = ?don?t care? 4. write command not allowed else t ras would be violated. see table 14, electrical characteristics and recommended ac operating conditions, on page 43 enable auto precharge t ch t cl t rp t ras t rcd t rc dqmu, dqml cke clk a0-a9, a11 dq ba0, ba1 a10 t cmh t cms t ah t as row row bank bank row row bank t wr d in m command t cmh t cms nop 3 nop 3 nop active nop 3 write nop active t ah t as t ah t as t dh t ds t ckh t cks nop nop column m 2 t0 t1 t2 t4 t3 t5 t6 t7 t8 t9 don?t care t ck
128mb: x16, x32 mobile sdram 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobile_2.fm - rev. g (draft) 7/04 en 64 ?2001 micron technology, inc. all rights reserved. figure 51: alternating bank write accesses note: 1. for this example, the burst length = 4. 2. x16: a9 and a11 = ?don?t care? x32: a8, a9,and a11 = ?don?t care? see table 14, electrical characteristics and recommended ac operating conditions, on page 43 don?t care t ch t cl clk dq d in m t dh t ds d in m + 1 d in m + 2 d in m + 3 command t cmh t cms nop nop active nop write nop nop active t dh t ds t dh t ds t dh t ds active write d in b t dh t ds d in b + 1 d in b + 3 t dh t ds t dh t ds enable auto precharge dqmu, dqml a0-a9, a11 ba0, ba1 a10 t cmh t cms t ah t as t ah t as t ah t as row row row row enable auto precharge row row bank 0 bank 0 bank 1 bank 0 bank 1 cke t ckh t cks d in b + 2 t dh t ds column b 2 column m 2 t rp - bank 0 t ras - bank 0 t rcd - bank 0 t t rcd - bank 0 t wr - bank 0 wr - bank 1 t rcd - bank 1 t t rc - bank 0 rrd t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t ck
128mb: x16, x32 mobile sdram 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobile_2.fm - rev. g (draft) 7/04 en 65 ?2001 micron technology, inc. all rights reserved. figure 52: write ? full-page burst note: 1. x16: a9 and a11 = ?don?t care? x32: a8, a9,and a11 = ?don?t care? 2. t wr must be satisfied prior to precharge command. 3. page left open; no t rp. see table 14, electrical characteristics and recommended ac operating conditions, on page 43 t rcd dqmu, dqml cke clk a0-a9, a11 ba0, ba1 a10 t cms t ah t as t ah t as row row full-page burst does not self-terminate. can use burst terminate command to stop. 2, 3 ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) full page completed don?t care command t cmh t cms nop nop nop active nop write burst term nop nop ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) dq d in m t dh t ds d in m + 1 d in m + 2 d in m + 3 t dh t ds t dh t ds t dh t ds d in m - 1 t dh t ds t ah t as bank ( ) ( ) ( ) ( ) bank t cmh t ckh t cks ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) 512 (x16) locations within same row column m 1 t0 t1 t2 t3 t4 t5 tn + 1 tn + 2 tn + 3 t ch t cl t ck
128mb: x16, x32 mobile sdram 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobile_2.fm - rev. g (draft) 7/04 en 66 ?2001 micron technology, inc. all rights reserved. figure 53: write ? dqm operation note: 1. for this example, the burst length = 4. 2. x16: a9 and a11 = ?don?t care? x32: a8, a9,and a11 = ?don?t care.? see table 14, electrical characteristics and recommended ac operating conditions, on page 43 don?t care t rcd dqmu, dqml cke clk a0-a9, a11 dq ba0, ba1 a10 t cms t ah t as row bank row bank enable auto precharge d in m + 3 t dh t ds d in m d in m + 2 t cmh command nop nop nop active nop write nop nop t cms t cmh t dh t ds t dh t ds t ah t as t ah t as disable auto precharge t ckh t cks column m 2 t0 t1 t2 t3 t4 t5 t6 t7 t ch t cl t ck
128mb: x16, x32 mobile sdram 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobile_2.fm - rev. g (draft) 7/04 en 67 ?2001 micron technology, inc. all rights reserved. figure 54: 54-ball vfbga (8mm x 8mm) note: 1. all dimensions in millimeters. ball a1 id 0.65 0.05 seating plane 0.10 c c 1.00 max ball a9 0.80 typ 0.80 typ 3.20 0.05 6.40 8.00 0.10 4.00 0.05 solder ball diameter refers to post reflow condition. the pre-reflow diameter is 0.42. 54x ?0.45 0.05 solder ball material: 62% sn, 36% pb, 2% ag solder mask defined ball pads: ?0.40 mold compound: epoxy novolac substrate material: plastic laminate 6.40 3.20 0.05 4.00 0.05 8.00 0.10 c l c l ball a1 id ball a1
128mb: x16, x32 mobile sdram 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobile_2.fm - rev. g (draft) 7/04 en 68 ?2001 micron technology, inc. all rights reserved. figure 55: 90-ball vfbga (8mm x 13mm) note: 1. all dimensions in millimeters. 2. recommended pad size for pcb is 0.4mm0.025mm. ball a1 id 1.00 max mold compound: epoxy novolac substrate material: plastic laminate solder ball material: 62% sn, 36% pb, 2% ag or 96.5% sn, 3%ag, 0.5% cu solder mask defined ball pads: ?0.40 13.00 0.10 ball a1 ball a9 ball a1 id 0.80 typ 0.80 typ 6.50 0.05 8.00 0.10 4.00 0.05 3.20 0.05 5.60 0.05 0.65 0.05 seating plane c 11.20 0.10 6.40 0.10 c 90x ?0.45 0.05 solder ball diameter refers to post reflow condition. the pre- reflow diameter is ?0.42 c l c l
128mb: x16, x32 mobile sdram 09005aef8071a76b micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16x32mobile_2.fm - rev. g (draft) 7/04 en 69 ?2001 micron technology, inc. all rights reserved. ? 8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-3900 e-mail: prodmktg@micron.com, internet: http://www.m icron.com, customer comment line: 800-932-4992 micron, the m logo, and the micron logo are trademarks and/or service marks of micron technology, inc. all other trademarks are the property of their respective owners. figure 56: 54-pin plastic tsop (400 mil) note: 1. 1. all dimensions in millimeters. 2. 2. package width and length do not include mold prot rusion; allowable mold protrusion is 0.25mm per side. see detail a 0.80 typ 0.71 10.16 0.08 0.50 0.10 pin #1 id detail a 22.22 0.08 0.375 0.075 1.2 max 0.10 0.25 11.76 0.20 0.80 typ 0.15 +0.03 -0.02 0.10 +0.10 -0.05 gage plane plastic package material: epoxy novolac lead finish: tin/lead plate package width and length do not include mold protrusion. allowable protrusion is 0.25 per side.

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